阐述一种射频有源识别系统的组成,采用的RFID技术标准、防碰撞算法和信息安全保障的技术,探讨系统的设计,包括标签、阅读器的硬件构架设计,模块电路,标签、阅读器、控制终端的软件设计.在对该系统进行硬件系统、读写距离、安全认证和防碰撞性能的测试后,结果表明达到设计目标,且具有较好的防碰撞特性.

针对制造业中待加工物品管理效率低下的问题,设计了一套基于射频识别(RFID)的智能货架管理系统.通过RFID阅读器和手持式智能终端实时进行数据采集,采用复杂事件处理(CEP)进行数据清洗、过滤并传入制造企业生产过程执行系统(MES).基于ISO15693协议对RFID阅读器实现发送功率可调、网口通信功能设计,借助.NET平台开发RFID中间件程序及网络应用程序,方便用户实时查询物品信息.系统已在制造企业中应用,效果卓著,性能良好.经实际测试,系统能够快速、稳定、高效地工作,实现了对待加工物品的实时监测和生产计划的高效执行.

提出一种基于国标空中接口协议GB/T28925的2.45GHz射频识别(RFID)读写系统设计,介绍阅读器和有源标签的硬件和软件系统设计。阅读器是基于ARM Cortex-M3内核处理器设计的远距离阅读器,阅读器通过串口或以太网与上位机通信,标签采用超低功耗芯片实现,解决标签耗电大的问题,借助C#完成控制终端的开发平台设计。采用成帧二进制树算法提高标签防碰撞性能,提高系统对标签的识别率,测试结果表明,阅读器能够快速、稳定、高效地识别标签。

针对PR9200芯片的超高频、无线射频识别读写器通信效率低下的问题,设计了一种基于FPGA的通信方案.介绍了数据通信的架构,制定了通信协议的传输规则,采用工业以太网口通信,并通过FPGA对传输的数据进行并行处理后送至MCU.仿真与测试验证表明,该读写器通信系统能有效地提高数据传输及处理速度,与原系统相比,通信效率提高了57％,且不影响系统稳定性,可应用于高速的标签识别中.

The problem of anti-collision is an important research topic in UHF RFID system. In order to further improve the recognition efficiency of RFID system, a new anti-collision algorithm based on collision slots elimination is proposed. The algorithm sends a new command through the reader to filter the tags of the collision slot one by one, making the tags in the collision slot further identified, that can avoid tags in the collision slot to enter the next frame recognition. Because the tags of collision slot are identified, the number of frame slots is reduced, and the coordination time in the recognition process is saved. Finally, the theoretical analysis and simulation results show that the new algorithm, based on the ISO 18000-6C protocol, reduces the recognition time by about 25% and improves the recognition rate by about 27% compared with the 18000-6C protocol.

为了解决超高频射频识别读写器在碰撞时隙标签无法识别的问题,本文遵循ISO18000-6C协议标准设计了一款高性能的超高频读写器系统,并对读写器的主要性能指标进行了仿真与测试,最后验证了设计的可行性.本系统采用模块化设计,系统工作频率为860-960 MHz,输出功率可达+30 dBm.通过引入新型防碰撞算法,使得读写器在碰撞时隙也可以一一识别标签,相比于现有读写器,标签的识别时间降低了约29％,标签识别率提高了约25％.

Vehicular ad hoc network (VANET) is a dedicated network to connect vehicles without any centralized administration or infrastructure. The wireless access in vehicular environments (WAVE) protocol leveraging IEEE 1609/802.11p is widely implemented for VANETs. However, in congested traffic situation, the performance of the WAVE system degrades significantly due to serious collision, especially for safety related broadcast services on the control channel (CCH) interval due to the inherent drawback of its collision avoidance mechanisms called carrier sense multiple access with collision avoidance (CSMA/CA). In this paper, we propose a method that can decrease the number of frame collisions in CCH with a few modifications to the IEEE 802.11p protocol. In the paper, vehicles still employ CSMA/CA to compete for the channel access opportunity. However, by taking advantage of periodicity of synchronization interval, a two-state switching scheme introducing two new inter frame space (IFS) is proposed to reduce the number of competing vehicles substantially and as a result, the collision probability is significantly decreased. The simulation results demonstrate the superiority of the proposed method in packet collision rate.

In order to solve the problem of retained surgical items (RSIS),the paper proposed a radio frequency identification (RFID) operating device management system based on ISO15693 electronic tags.In the system,every surgical device contains an ISO15693 electronic tag,and the RFID reader with three channels is cooperated to achieve the surgical instruments' registration,recycling and scanning.The upper computer' s operation interface of the operating device management system is designed by using Qt GUI application development framework.Experiments show that the system can stably,accurately and timely accomplish the intelligent management of the operation devices' using and recycling,the problem of RSIS is prevented.The system can provide more reliable safeguard for the safety of operation.System now has the capability of practical application and is going on the medical application promotion.

Aimed at solving the low efficiency problem of the tests of RFID wafer based on ISO/IEC 15693 protocol,the author came up with a method of a 16-channels parallel test system.It uses FPGA (field programmable gate array) as the MCU (microcontroller unit) and parallel method to make the logical function accurate and efficient.The dedicated hardware circuit is designed with low-cost and targeted usage.The 16-channels parallel test system can substantially improve test efficiency.This system innovatively uses method of direct coupling test technology,can completely simulate actual working condition of DUT to make sure the consistency of test results and actual results.Using 8 inches wafer as an example,the author took 36 hours finishing the work by single channel serial test system and 2.26 hours by the 16-channels parallel test system.The result shows parallel test system can save time as 93.8％,hence it greatly raises the test efficiency and reduces the test time.

This paper presents a verification technology based on coverage-driven stimulus generation algorithm . A completed verifi-cation platform is given , and applied to a high frequency RFID ( Radio Frequency Identification ) chip successfully . The main idea of this technology is obtaining the boundary conditions and modifying the constraint of stimulus generation by analyzing function cover-age and code coverage , and then using the new stimulus to verify the boundary conditions . So the coverage is up . After taping out , the verified chip by this verification platform was be tested. The test shows that all function are correct and performance is excellent.

介绍了一种基于UVM(Universal Verification Methodology)验证方法学的验证平台.该验证平台是针对基于自主知识产权的国产MCU C0的CPU卡芯片的功能验证需求所搭建的.该验证平台采用面向对象的层次化的建模方法,完成了符合ISO14443协议的验证事务,通用功能验证组件以及设计参考模型的建模;能实时监测设计中信号的变化,能实现在验证过程中验证结果的自动对比,能根据覆盖率调整验证的进程.验证结果表明,该验证平台具有复用性,提升了芯片验证的效率和可靠性.

针对目前超低功耗温度传感器误差大的问题,运用由精确比例电流源偏置的寄生衬底PNP晶体管,采用0.18 μm混合信号工艺设计了一种可集成于无源RFID标签的新型高精度温度传感器.传感器核心电路产生与绝对温度成正比的电压信号,通过新型开关电容积分器进行放大,并由改进的12位超低功耗逐次逼近模数转换器完成数字量化.仿真结果表明,单次温度转换时间为4.25 ms;在1.8V工作电压下,平均电流为17.5 μA;在-37℃～91℃范围内,温度误差为-0.1℃～0.43℃.

设计了一种降压型LED恒流驱动芯片.该芯片采用电流滞环控制技术对输出电流进行恒流控制,实现输出高达2 MHz的开关频率.通过比较外部反馈电阻上的压降与芯片内部的滞环电压,使输出电流的波形为滞环变化三角波.采用了全新的自适应滞环电压产生电路,以补偿芯片内部的延时,实现了在2 MHz的开关频率下小于3％的恒流精度.该LED恒流驱动芯片采用ASMC 0.35 μm 5 V/60 V BCD工艺,工作电源电压范围为5～60 V,最高工作频率为2 MHz,典型平均输出电流为700 mA.该芯片具有PWM调光功能,通过DIM信号的占空比来调节LED的亮度.

This paper presents a new verification platform .Suite for decoder system of ultrahigh frequency RFID , the new platform is based on the method of UVM (Universal Verification Methodology ) .Compared to traditional verification platform ,the new verification platform has many advantages ,such as stronger reuse and extensibility , more reasonable hierarchical structure ,higher efficiency and verification automation .And the platform is coverage‐driven .Significantly ,it enhances the efficiency and quality of verification .Now the verification platform has been successfully applied to the design and verification of decoder system in an ultrahigh frequency RFID tag chip .The verification report shows that coverage is expected and meet the requirement .

针对高频射频识别(RFID)晶圆在中测(CP)阶段单通道串行测试效率低下的问题,设计了一种基于现场可编程门阵列(FPGA)的多通道并行测试系统以提高测试效率.鉴于RFID晶圆上没有集成天线,提出了一种新的基于探针技术的射频耦合式的晶圆检测方法,模拟芯片实际工作.系统选用FPGA为微控制器,配以多路射频耦合通信电路,实现测试向量生成及快速信号处理.再结合上位机与探针台高速并行的通用接口总线(GPIB)通信接口,以实现晶圆级RFID芯片测试.经实际测试,该系统能够实现16通道并行测试,与单通道串行测试系统相比,效率提升了97％,可靠性好,稳定性高,可应用高密度RFID晶圆的中测.

Three ideas of decoding the modified miller code were proposed.The advantages and disadvantages in the practical applications were analyzed to improve the recognition ability for decoding the modified miller code.According to the simulated results and the actual test results,the decoding effectiveness for the modified miller code was consistent with that of the protocol.One of the decoding method based on period sampling was applied to Type A card,which had brought about a good result in the practical application.

提出了一种基于ISO/IEC15693协议的标签芯片编解码系统设计的实现方法,使编解码更加完整准确.采用Verilog HDL建立RTL模型,用ModelSim进行功能仿真,并在Altera DE2-115与射频前端搭建的平台上进行了FPGA验证.最后不仅功能验证正确,而且比协议中要求的识别凹槽宽度范围广,处理更加灵活,同时减小了射频前端模拟解调的压力.对其他编解码系统的实现也有一定的借鉴意义.

In light of the small scale,limited time and expenses of CPU card design,by selecting a proper bus interconnection structure on chip we design a set of virtual prototype verification platform.The principle of virtual prototype verification platform is introduced in the paper,the highlight is put on analysing the use of chip bus structure of AHB-lite which can dramatically reduce the complexity of CPU card design.The constructed virtual prototype verification platform of CPU card is employed to test the architecture of CPU card and the self-designed IP modules,and the whole architecture is tested on practical physical prototype verification platform as well.Test results indicate that the designed virtual prototype verification platform can substantially reduce the design time and expense.

Passive RFID tag system requires low-power consumption. In this paper, the clock shutdown technology was been used to reduce power consumption and the module re-used was been used to reduce chip area. The design was been described for the digital part of RFID tag chip based on ISO/IEC15693 standard, that was including decoder, encoder, CRC generation and verification, EEPROM interface block ,the master state machine and clock management block. The detailed design scheme about the master control block, Conflict part and coding block was been given. The unique coding was been used and state machine design scheme was been used in all blocks, which would not only simplify the design, but make the design more flexible. And EEPROM RTL model was been built-in for test validation. Finally, the results were verified correctly in the specified clock frequency in device in DE2- 115FPGA Altera kit using Verilog in RTL level.

A new type of silicon semiconductor temperature sensor applied for RFID tag chip is designed based on the linear temperature characteristic of base-emitter voltage of parasitic substrate PNP transistor. A novel switched capacitor integrator based on positive-negative synchronous integration is introduced to amplify the weak temperature signal precisely and provide a method to represent the temperature in analog domain. Temperature quantization is accomplished by a 12-bit ultra-low-power successive approximation analog-to-digital converter providing a resolution of 0.03125°C/LSB. The circuit was simulated by using device model of 0.18-μm CMOS process. The output integration swing is 2VPP and the average current dissipation is 38.91μA at 1.8V supply. The sensor achieves an accuracy of -0.1°C to +0.33°C in the temperature range of -39°C to 89°C.