It is of great significance to study the response mechanism and performance improvement strategy of bismuth telluride(Bi2Te3)photoelectric detector in long-wave infrared band.Firstly,through selection of the growth temperature zone during chemical vapor deposition(CVD),the thermodynamically-led morphology controlled synthesis of nanostructures was achieved,and the shape was changed from tri-angular nanosheets to nanowires.It is revealed that the long-wave infrared photoresponse of Bi2Te3 nanowire photoelectric detector is dominated by the photothermoelectric effect.Through the optimization of electrode material,the responsivity of the detector is improved to 17 V/W,and the noise equivalent power is 0.22 nW·Hz-1/2.The asymmetric electrode structure was constructed to solve the problem that the micro-nano photothermoelectric detector has no response voltage output under global light illumination.In addition,the Bi2Te3 nanowire photothermoelectric detector exhibits a short response time of 53 μs,breaking the limit of millisecond response speed of traditional thermal photoelectric detectors.Compared with other complex structural designs,the Bi2Te3 nanowire photoelectric detector has comparable per-formances,which provides a new idea for the design of two-dimensional photothermoelectric detectors.
In the context of the nuclear resonance scattering experiment within the high-resolution spectroscopy line station system(HEPS-B5)of the high energy photon source,in order to meet the time measurement demands of high-resolution time-to-digital conversion at the picosecond level for test sam-ples,a four-channel interpolated delay chain time-to-digital converter(TDC)chip based on SMIC 180 nm process was developed.The TDC chip utilized an interpolated delay chain method with a chain structure that combining both"coarse counting"and"fine counting"to improve measurement resolution,and combined with a clock counter to achieve a wider dynamic measurement range.In order to prevent the transmission of metastable states,a two-stage inverter was employed as the basic delay unit,and the data was safely transferred between different clock domains though an asynchronous first-in-first-out(FIFO)buffer.Experimental test results demonstrate that the TDC chip offers a time resolution of 56.3 ps and a dynamic measurement range spanning from 0 to 262 μs,effectively meeting the high-precision time mea-surement requirements for nuclear resonance scattering experiments.
In order to predict interconnect short circuit and open circuit failures of multi-chip modules(MCMs),ANSYS parametric design language(APDL)was used to realize the three-dimensional automatic modeling for a highly integrated dual-channel MCM consisting of two Si switch chips and two GaAs low noise amplifier chips.The heat conduction analysis of the MCM under different working conditions was carried out.Based on the theory of atomic flux divergence(AFD),the interconnect reliability for the MCM under different operating temperatures and voltages was analyzed by the finite element analysis(FEA)method.AFD distribution and temperature distribution of the MCM under different working conditions were obtained,as well as the relationship curves of temperature,AFD and operating voltages.The results show that the temperature of chips and plastic sealing material increases with the increase of the operating voltage.Meanwhile,the interconnect reliability decreases dramatically with the rising of temperature and operating voltage.The research results can provide reference for the layout design for MCMs to ensure the interconnect reliability.
For power MOSFETs,whether a smaller source-drain leakage current can be obtained at a high external voltage is one of the important indexes for evaluating device performance.To solve the problem of excessive source-drain leakage current of shield gate trench MOSFET with a breakdown voltage of 150 V,two effective optimization methods were proposed,including lowering the rapid annealing tem-perature after ion implantation and reducing the Ti adhesion layer thickness of contact hole.Combined with the theoretical calculation,the reasons for the reduction of leakage current via above methods were analyzed from the angle of influence of defects.By using these two methods,the defect concentration near pn junction in source region is reduced,resulting in a smaller reverse current generated by pn junction,thus reducing the leakage current and effectively solving the problem of large source-drain leakage cur-rent,which improves the yield of the product.
Shield gate trench(SGT)MOSFET was used as the research object to study the pheno-menon and physical mechanism of single particle microdose effect induced by heavy ions.Heavy ion irradiation test on 30 V SGT MOSFET at different bias voltages was carried out,and the changing trend for the transfer characteristic curves of the device after heavy ion radiation was analyzed to reveal the deg-radation rule of single particle microdose effect.It is found that heavy ion incident will cause the increase of subthreshold current and lead to negative drift of threshold voltage,and the negative drift of subthreshold voltage is more serious under negative gate voltage.Experimental results combined with TCAD simulation further reveal that the positive oxide trap charge at the Si/SiO2 interface of the gate ox-ide side wall is the main reason for the degradation of device threshold voltage and subthreshold voltage.The results can provide guidance for the evaluation and modeling of single particle microdose effect of SGT MOSFET.
The low blocking voltage,poor temperature characteristics and low short-circuit reliability of Si super junction lateral double-diffused metal oxide semiconductor field effect transistor(SJ-LDMOSFET)can be effectively improved by the Si/SiC SJ-LDMOSFET.The short-circuit and tem-perature characteristics of Si SJ-LDMOSFET and Si/SiC SJ-LDMOSFET were studied by TCAD software.When the ambient temperature raises from 300 K to 400 K,the maximum temperature in Si/SiC SJ-LDMOSFET is lower than that of Si SJ-LDMOSFET,exhibiting good ability to suppress self-heating effect,the breakdown voltage of the Si/SiC SJ-LDMOSFET remains almost unchanged,and the saturation current degradation rate is lower.In the case of short-circuit,the internal maximum tempera-ture rise rate of the Si/SiC SJ-LDMOSFET is significantly slower than that of Si SJ-LDMOSFET.Com-pared with the Si SJ-LDMOSFET,the short-circuit maintenance time of Si/SiC SJ-LDMOSFET is increased by 230％and 266.7％at the ambient temperature of 300 K and 400 K,respectively.The research results reveal that the Si/SiC SJ-LDMOSFET has better temperature stability and short-circuit resistance capability at high temperatures,and it is suitable for environment with high temperature,high voltage,and high short-circuit reliability requirements.
The coupling effect rules of three reinforcement methods such as screw fastening,under-filling and local dispensing on the reliability of ball grid array(BGA)solder joints under temperature cycles and random vibration conditions were analyzed by establishing the finite element model of device and printed board assembly around the BGA package device reinforcement.The results show that under the stasic stress,compared with local dispensing reinforcement method,the underfill method will transfer the deflection caused by screw fastening to all solder joints,making the overall static stress of solder joints at a high level.Under the temperature cyclic stress,the influence of reinforcement method on the thermal stress of solder joints is greater than that of screw position for the same mounting distance,and the four-corner L-shape dispensing reinforcement method has lower thermal stress of solder joints.Under the vibration stress,both screw fastening and local dispensing reinforcement methods have positive effect on reducing random vibration stress.When the screw position and dispensing reinforcement position are cross-distributed,the vibration resistance is the best.The research results can provide reference for the structural design and reinforcement process design of BGA printed board assembly.
Gallium oxide(Ga2O3)is one of the most ideal semiconductor materials for the prepara-tion of high voltage and high power devices due to its excellent characteristics such as ultra-wide bandgap,high theoretical breakdown electric field strength,and high Baliga's figure of merit(BFOM).However,realizing good surface passivation of devices especially improving interfacial properties of insu-lator/Ga2O3 is still a key technical issue in the development of Ga2O3 devices.Firstly,the research pro-gress in surface passivation and high-k dielectric energy band engineering of Ga2O3 metal-oxide-semicon-ductor(MOS)devices is analyzed and compared.Then,the essential research progress of surface passi-vation technology for Ga2O3 devices(transistors and diodes)is reviewed,including surface edge termi-nation design,multi-passivation process,perovskite oxide passivation,etc.Finally,the research directions of Ga2O3 device surface passivation are prospected.
JESD204B(abbreviated as 204B)is an important interface for connecting high-speed analog-to-digital/digital-to-analog(AD/DA)conversion in intelligent signal processing system-on-chips(SoCs).When integrating SoC system structure with 204B standard requirements,adaptive buffer struc-ture(ABS)can compensate the imperfect of 204B protocol that lack of flow control for data transmission,and by setting up adaptive buffer and flow control mechanism,data transmission reliability can be guaranteed.Verified by field-programmable gate array(FPGA),the SoC can achieve a data transmission bandwidth of 4×12.5 Gbit/s at 204B interface,proving the feasibility and validity of the designed 204B interface scheme in the intelligent signal processing SoC,and meeting the requirements of the intelligent signal processing SoC for data interface.The implementation of the scheme is useful for integrating flowless control data transmission protocols with SoC structures.
High temperature microelectromechanical system(MEMS)dynamic pressure sensors are commonly used for dynamic testing in harsh environments,and their stable operation is limited by reliable packaging.The influences of different packaging adhesive layer materials on the static and dy-namic characteristics of sensors were studied through finite element simulation software.The simulation results show that the sensor with inorganic high temperature adhesive as the adhesive layer material has a natural frequency of 488.68 kHz and a rise time of 60 μs at room temperature,and a sensitivity of 73.41 mV/MPa at 600 ℃,which has certain advantages in dynamic performance such as impact interference resistance and response time compared with sensors using epoxy resin and glass adhesive layer materials.Measurement results show that from room temperature to 300 ℃,the zero point output voltage of the sensor with inorganic high temperature adhesive as the adhesive layer material increases from 2.16 mV to 7.45 mV,and the full scale output voltage decreases from 124.0 mV to 69.35 mV,which has the same trend with simulation results.The results can provide reference for the selection of adhesive layer materials in the packaging process of SiC high temperature pressure sensors.
With the continuous scaling of devices in integrated circuits,RC delay has become the main factor limiting circuit operating frequency.As one of the milestones in the development of back end processe,RC delay can be significantly decreased by introducing copper(Cu)and low dielectric constant(κ)materials as interconnect conductor and dielectric materials.However,as process technolo-gy node reaching 5 nm or lower,the size effect of resistance makes Cu interconnect technology impossible to meet performance requirments.Due to limitations of 1ow-κ materials in process integration,the RC delay caused by scaling is primarily suppressed through metallization.Developments and challenges of metal interconnect technology are introduced.The latest research progress of metal interconnect technology to solve the problems in recent years are summarized,including the development of new processes and materials to optimize conventional diffusion barrier/cushion layers,Ru semidamascene process and hybrid metal interconnect process.And the development of metal interconnection technology in the post Moore era is prospected.
The leakage current of integrated circuit(IC)chips is one of the main factors restricting chip power consumption,performance and lifetime.Due to the complexity of the chip manufacturing process,the chip leakage current distribution between the edge and the central region of the wafer is often uneven,and the chip leakage currents between different wafers are quite different.In order to solve these problems,through the analysis of the correlation between chip leakage currents,electrical parameters and gate dimensions,it is found that the particularity of the mechanical structure of the etching equipment can cause the difference in chip gate dimensions between the edge and central region of wafers,resulting in the difference of regional leakage currents.The sub-regional ion implantation method was used to solve the problem of uneven chip leakage current distribution in the wafer,thereby improving the yield.At the same time,the process-electrical joint-control method was used to reduce the larger chip leakage current difference between different wafers.It is verificated through actual cases that the use of sub-regional ion implantation method can increase the yield by about 30％,and the process-electrical joint-control method can reduce the difference in chip saturation current between wafers by 61％.
金属钴的电阻率较低,是芯片制造先进工艺节点的关键互连材料.电沉积具有自下而上的生长特点,是优异的钴沉积工艺.为达到理想的钴电沉积的效果,必须了解电化学反应机理以及电流密度和抑制剂对该机理的影响.通过恒电流电沉积法,在硫酸钴-硼酸体系中,研究了不同电流密度对电沉积得到的钴薄膜形貌、晶体结构、电阻率等的影响.并且分析了含亚氨基抑制剂分子苯并咪唑(BZI)和2-疏基苯并咪唑(MBI)对钴电化学反应的抑制作用,探究其对钴薄膜形貌、晶粒尺寸和电阻率的影响.结果表明,无抑制剂时,钴晶粒以Co(002)为主;BZI的抑制能力强于MBI;由于BZI的抑制能力过强,无法沉积完整的钴薄膜;抑制剂MBI的加入会增强钴薄膜晶体的(101)晶面的取向.
针对液晶显示器(LCD)芯片中各模块不同的负载与供电需求,同时为了兼容更多同类型LCD驱动控制电路,设计并实现了一种高精度可调电压产生电路.该电路以零温漂基准电压电路为核心,由低压差线性稳压器(LDO)、电荷泵等组成.在温度检测电路与8 bit模数转换器的协同作用下,配合数字模块的设置值得到放大系数,并用于LDO模块得到最终的驱动电压.通过仿真得到,当电源电压(VDD)大于1.72 V时,带隙基准电压(Vref)可稳定在1.23 V;温度为-20～80℃ 时,Vref 的斜率为±15 μV/℃;电荷泵在3.3 V的输入电压下输出电压为19.794 V,满足6倍的升压范围且效率满足既定目标.采用0.18 μm CMOS工艺流片并对其进行测试,与仿真结果相比,实测结果存在部分因工艺模型导致的误差,但差值均在±10％的误差许可范围内,表明了此电路的可行性和实用性.
室温Ga基液态金属兼具金属的导电性和液体的流动性,是柔性电子器件的首选材料.在电子产品微型化趋势下,Ga基液态金属导体面临着更大的电流密度、更高的焦耳热效应等问题,严重影响着液-固电极界面的微观结构及结构稳定性.利用实验数据与数值模拟相结合的方法,通过改变通电过程中的换热介质研究了焦耳热对Cu/Ga-21.5In-10Sn/Cu液-固电极界面微观结构演化的影响.结果表明,在400 A/cm2的电流密度下通电24 h后,Cu/Ga-21.5In-10Sn/Cu界面会生成CuGa2,阴极和阳极界面生成的CuGa2层厚度没有显著差异,并且在阴极Cu电极表面出现明显的溶蚀坑,表现出极性效应,而且通电过程中产生的焦耳热会导致阴极Cu电极表面溶蚀坑的快速生成.
界面电阻是半导体器件制备和性能表征的一个重要参数.针对金属-半导体互连块体样品的界面电阻测量,利用Keithley2450型数字源表、自制夹持力可视化夹具、运动控制卡、直线模组等搭建了基于扫描探针法的界面电阻自动测试装置,并在LabVIEW下开发了测试软件.改变了传统扫描探针法的驱动方式,即使用直线模组驱动样品进行微步距移动,探针仅做上下运动,实现了扫描探针法电阻测试,节约了硬件成本.选用Keithley2450型数字源表,使得可在输出恒电流的同时进行电压测量,且其自带输出回读功能,简化了测试装置并提高了测量数据的准确性.通过对块体Cu-Bi2Te3金属-半导体焊接样品进行界面电阻测量,验证了测试装置的稳定性和可重复性.
针对功率模块焊料层在热循环载荷及随机振动载荷下的可靠性问题,利用ANSYS Workbench对简化模型进行热模态和随机振动仿真分析,预测功率模块在热振耦合下的疲劳寿命.根据改进的Coffin-Manson模型预测功率模块在热循环载荷下的疲劳寿命;利用Coffin-Manson 高周疲劳经验模型预测功率模块在随机振动载荷下的疲劳寿命;采用线性累积损伤叠加法预测功率模块在热振耦合下的疲劳寿命.研究结果表明,随着温度的上升,功率模块的固有频率逐渐降低;随着直接覆铜(DBC)上铜层厚度增加,基板焊接应力和芯片焊接应力会相应增加;随着DBC下铜层厚度增加,基板焊接应力呈增加趋势,芯片焊接应力先增加后减小;随着DBC陶瓷层厚度增加,基板焊接应力增大,芯片焊接应力减小.通过对热振耦合下功率模块的疲劳寿命计算分析可知,疲劳寿命主要受随机振动载荷影响.
为了准确预测芯片电路寿命,建立了 一种能成功双向预测CMOS器件寿命和器件老化程度的可靠性模型.结合改进的衬底电流方程、漏源电流和时间变量t,组建了 Age(t)模型.通过挑选合适的BSIM4模型参数,联合Age(t)方程构建指数函数关系式,建立了一种可植入EDA工具内的CMOS老化SPICE模型,并提出了可获得精确模型性能的参数提取方法.在静态持续加电条件下,单级器件的仿真结果与实验数据吻合良好,并且表现出对寿命和老化率的良好预测性.采用该模型对由3级反相器组建的环形振荡电路进行动态信号仿真,得到20年后电路输出波形,验证了模型的合理性.
个人热管理(PTM)技术通过调控人体表面的热学微环境,可实现对人体体温的精准调控,不仅可以维持人体热舒适,而且可以有效降低建筑能耗,是近年来的研究热点.基于银纳米线(AgNW)的柔性薄膜加热器件具有加热效率高、柔性可拉伸性强、佩戴舒适等优点,在PTM中得到了广泛应用.基于AgNW柔性薄膜加热器在PTM应用中的研究进展,从AgNW合成、成膜、后处理与封装4个方面,对AgNW柔性薄膜加热器的制备工艺进行了全面总结;采用方块电阻和品质因子等参数定量分析了电热性能和透明度等关键指标的发展趋势;最后介绍了Ag NW薄膜加热器与电磁屏蔽、运动感应、NO2检测等应用的集成,并对其未来的发展方向进行了展望.
植物柔性传感器具有轻量化、透气、植物表面共形性高等特点,可以实现无损、实时、原位监测,提供精准的植物生理与环境信息,实现植物语言识别,开创"植物半导体新赛道".介绍了柔性电子技术在植物健康监测方面的最新进展,概述了植物柔性传感器用于植物激素、信号分子、植物电信号、挥发性有机物等的监测,可有效反映出植物健康状态;通过监测地表和空气中植物代谢产物反映环境胁迫条件,分析了新型植物可穿戴设备的传感技术,制备材料、结构以及监测方法.最后,对植物柔性传感器在现代农业中的应用进行总结,并讨论了未来植物可穿戴设备面临的机遇和挑战.
