The annealing of amorphous TiO x films obtained by electron-beam evaporation under atmospheric conditions at temperatures from 300 to 400°C is found to lead to the formation of an anatase crystalline phase. According to Raman spectroscopy data, the increase in the fraction of the crystalline phase stops at an annealing temperature above 350°C. According to the results of X-ray diffraction analysis, the average crystallite diameter is about 23 nm. Electron-microscopy studies show that, upon annealing, the surface layer (15 nm thick) crystallizes in the films, and TiO 2 nanocrystals with sizes from 4 to 10 nm are formed in the bulk. As the depth increases, the number of nanocrystals decreases.

Hexagonal silicon polytypes have attracted significant attention within the scientific community due to their potential applications in next-generation electronics and photonics. However, obtaining stable heterostructures based on cubic and hexagonal polytypes is a challenging task. This study demonstrates the synthesis of thin layers of the hexagonal phase of silicon, specifically 9R-Si, using a conventional microelectronics technique—ion implantation. Implantation of Kr ^+ ions was performed through a SiO _2 layer, with thickness approximately twice the projected range of Kr ^+ ions, followed by high-temperature annealing. High-resolution transmission electron microscopy revealed that damage to Si substrate at the SiO _2 interface resulted in the formation of a thin amorphous layer, which recrystallized during annealing, leading to the formation of the 9R-Si polytype. It is presumed that mechanical stresses induced by implantation through the oxide layer promote hexagonalization during subsequent high-temperature annealing. The effectiveness of hexagonalization was found to depend on the substrate orientation. In addition to the formation of the 9R-Si phase, under the utilized implantation and annealing parameters, silicon exhibited light-emitting defects, with photoluminescence observed at a wavelength of approximately ∼ 1240 nm up to temperatures of about ∼ 120 K. The obtained results may find applications in silicon micro-, nano-, and optoelectronics.

III–V/Ge/Si(001), III–V/Ge/SOI(001), and III–V/GaAs(001) heterostructures are fabricated and investigated. The Ge buffer layer for the III–V/Ge/Si structure is grown by vapor deposition onto a Si(001) substrate via the decomposition of monogermane on a “hot wire”. In the case of III–V/Ge/SOI, the Ge buffer layer is obtained on a SOI(001) substrate by molecular-beam epitaxy via two-stage growth. The III–V layers are grown by metalorganic chemical-vapor deposition. It is shown that Ge/SOI formed by molecular-beam epitaxy using two-stage growth allows the fabrication of III–V layers that are highly competitive with those formed on Ge/Si in terms of crystalline and optical quality.

AIIIBV/Ge/Si (001), AIIIBV/Ge/SOI (001), and AIIIBV/GaAs (001) heterostructures were formed and investigated. The Ge buffer layer was produced by the "hot wire" technique on a Si substrate (001) for the AIIIBV/Ge/Si structure. In the case of the AIIIBV/Ge/SOI, the Ge buffer layer was grown on the SOI (001) substrate by molecular beam epitaxy via two-stage growth. The growth of AIIIBV layers were performed by metalorganic chemical vapor deposition. It is shown that the Ge/SOI formed via two-stage growth allows the growth of AIIIBV layers that are not inferior in structural and optical quality to those formed on the Ge/Si.