An algorithm and a technique are developed for finding the maximum values of the target current components in a MOS transistor with an n-type built-in channel depending on the submicron and nanoscale topological norms for a frequency transformer in the presence of intensive noise at its input. The spectral making components of the intermediate frequency are evaluated and analyzed for the given amplitudes of the generator, signal, and handicap. The behavior of the n-MOS transistors designed according to the GPDK045 and GPDK0990 technological norms is investigated.

The analysis of schematics solutions of frequency multipliers is carried out and the methodology of multipliers arrangement in the integral version is developed. The structure of suitable for implementation in technological basis with submicron topological norms filterless multiplier is justified, which fundamentally exceeds the best world achievements on the criterion of spurious harmonics level in the spectrum of the output signal.

Analytical expressions of transfer characteristics of n-МОП-and p-MOP-tranzistorov are received. The device of polynoms of Chebyshev is used. The technological basis with nanoscale design norms is realized

The technological basis of the technique GPDK 090 remote mode research in CMOS transistor level integrated combination of digital devices with nanoscale channel parameters

This article describes the development and implementation of the IBIS-models for high-frequency ultra-large of integral circuits (VLSI), A mathematical model for describing them. The expediency in IBIS of modeling digital devices. The estimation of the different CAD systems, allowing syntax check and assess the correctness of the IBIS-model

Analytical relations have developed an algorithm to determine the potential values of output current component in the modes of frequency multiplication MOSFET with arbitrary (within the limits of physical realizability) values of the parameters of the channel in the submicron technological base

It is offered and realized for a number of technological bases (ХС06, ХС035, ХС18 GPDK009) a design procedure of a marginal frequency efficiency of conversion for MOS transistor in submicron and deeply submicron bases with any (within design implementation) channel parameters

Structural and functional organization of 8-bit microcontroller with modificated AVR RISC architecture was designed

Designing of topology of Two Wire serial interface (TWI) was implemented in the technology LF150 (150nm). The topology block size is 226 х 211um

In article the problematics of designing of the analogue blocks used as in structure ULSI of type «system on a chip» and as separate independent products, with reference to submicronic KMOP-technologies reveals. The route and key rules of designing of analogue blocks with use CAD are resulted, recommendations about protection of blocks from internal and external influences are given

Article is devoted improvement of a cell of the parametrical multiplier of harmonious fluctuations for the purpose of its expansion broadbandness, to experimental researches of model of the cell created on the basis of the advanced scheme and model of a cell, constructed on the basis of its topology

The analysis of circuit decisions of devices of multiplication of frequency is carried out, the structure and construction suitable for realisation in technological basis with submicronic topological norms of a base cell of the multiplier without oscillatory systems which essentially surpasses the best world achievements in criterion of level of collateral harmonics on an exit of a doubler of frequency is proved

In information environment OrCAD V.9.Х with use of personal COMPUTERS principles of work of LC-oscillators on bipolar and field transistors are considered

In information environment OrCAD V.9.X are considered principles of work of detectors of the amplitude modulated fluctuations with use of personal computers