Besides the well-known pulse width modulation (PWM), different pulse-pattern generation techniques have been introduced since the invention of more performant control hardware. Especially if the switching-to-fundamental-frequency ratio is small, optimization-based pulse pattern yield to better performance than standard PWM modulation. The Assessment-Based Flux Trajectory Optimization (AFO) is a novel pulse-pattern generation algorithm, obtaining a very good performance in stationary and dynamic operation. In this paper, the AFO’s objective functions are analyzed in detail. Performance criteria have been introduced to compare different AFO configurations. Finally, a simulative method is introduced to parameterize the AFO according to the application-specific requirements.

This paper describes a procedure for determining parasitic inductances in a power module using frequency domain analysis, focusing on the current path and the resulting in-ductances. Subsequently, the results obtained are verified using a double-pulse test under realistic conditions. For this a model-based approach is chosen. With the help of a curve fit the oscillations due to a switching process are characterized. With the aid of the characteristics of the oscillations, lumped elements of the power module and a lumped elements equivalent circuit of the entire commutation loop can be found, including the parasitic capacitances associated to the commutation loop. The resulting model of the commutation loop is verified by further measurements.

The interface between control and powerelectronic converters is commonly an appropriate pulse-pattern generation. Well known concepts like PWM or synchronous pulse patterns have their limits in relative modulation degree or dynamics - a new approach called Assessment- Based Flux Trajectory optimization (AFO) provides excellent performance especially at a low ratio of switching frequency to fundamental frequency. The approach and its general principle will be introduced and the performance results will be compared to a classical PWM pulse pattern generation.

In many power electronic applications the request of short development time demands reliable simulation studies to prove the control concepts in early developments stages and avoid critical behavior in real application. Simulation studies are sufficient to prove the general behavior of a control code. However, the platform architecture of the target hardware influences control behavior and code stability. Real-time requirements also demand tests on the target hardware. Consequently, the whole control system including data acquisition, control algorithm and pulse pattern generation has to be tested. Hardware-in-the-Loop (HIL) tests are usually applied. They require expensive hardware and have some disadvantages caused by unavoidable delays. This paper combines the benefits of an Advanced Hardware in the Loop concept with a low-cost SoC based real-time platform. It presents a concept using SoC and dual Core architectures meaningful for real-time applications with a clear definition of responsibilities for each section resulting in a streamlined development process. A simulation test bench is introduced and the functionality is proven by measurement results.

High-Voltage DC (HVDC) transmission lines offer highly efficient transport of electric energy. If connected to comparatively weak AC grids, self-commutated converters are the proper choice, because they allow to stabilize the grid in case of faults by injecting reactive power. At high voltages of e.g. 400 kV Modular Multilevel Converters (MMC) fulfill all requirements. For testing all relevant aspects of a multiterminal HVDC transmission system, a scaled-down test bench has been built up. The associated real-life system "Ultranet" will use overhead lines. Weather-induced faults (lightning, conductor bouncing und strong wind) are expected and have to be mastered by the converter stations. This paper first introduces the system and the associated test bench and then presents the mitigation of faults caused by arcing.

Hardware in the Loop (HiL) supports development processes in many types of applications. Power electronic systems with switching frequencies up to several kilo hertz constitute some of the most demanding applications for the quantization time of the HiL. The non-avoidable delay forces very short calculation periods which lead to high effort in hardware and software implementation. For PWM based controllers it is possible to synchronize the HiL model to the control cycle and the PWM and so reduce the simulation effort to one calculation per control cycle. Simultaneously the usually unavoidable delay of the HiL calculation time is eliminated by implementing a special digital interface between control system and HIL system. Because of this interface the pulse patterns themselves are not needed by the HiL. Additional precise pulse pattern verification becomes viable. The concept is realized on a FPGA-ARM-SoC control platform and verified against measurement results from a physical test bench.

Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combine many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested - but to the knowledge of the author's seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

An identification of critical fault events within the power system enables situational awareness and the activation of corrective actions for HVDC systems. Recent publications deal with central implementation. This work proposes a local identification approach which is based on local measurements at the converter substations. The proposed methodology is introduced in detail subsequently. It is based on a comparison of online measurement and a pre-processed offline database. The application of characteristic fault patterns which are derived from the time domain signals simplifies the approach significantly. The influence of the HVDC converter stations during faulted operation is assessed as well as the impact of parameter deviation and inaccuracies of the offline simulation.

For model-based predictive control methods it is essential to predict the reaction of the whole system. Sampling of the converter-output-voltages needs unreasonably high sampling rates and is generally avoided. In consequence the converter behavior itself becomes a part of the model. This paper provides a theoretical description of the most relevant effects and gives guidelines for modeling the converter voltage error even for light-load cases correctly. The challenge is that the actual current waveforms including the switching harmonics determine the converter voltage error. In general switching harmonics are neglected on the control level. Therefore the theoretical description is based on characteristical values already available or predictable on the control level. The results are verified by simulation and test-bench measurement results.

Voltage-source converters need grid-side filters to connect to the grid. These grid-side filters on the one hand couple the converter-generated grid-side voltages to the grid voltages and on the other hand mitigate the influence of the switching of the power-electronic devices of the converter on the grid. While uncontrolled diode bridges usually couple via inductances (due to their low switching frequency defined by the grid frequency) self-commutated converters need more sophisticated filter structures, usually of LCL-type, to damp the effects generated by the switching of the power-electronic devices such, that EMC requirements imposed by grid codes are met. Such filters rely on resonance - and various types of resonances may lead to interactions between multiple converters connected to a grid, e.g. in case of solar farms. Resonance effects may lead to additional stress on components, additional losses in e.g. transformers, interruption of service and even damage to components. Consequently, damping of the filter is one option to improve the interoperability of a filter - but it needs additional components and causes cost and losses. This paper researches the effect of filter damping based on a demonstrative example.

Connecting renewable energy sources to the grid requires stable and reliable control algorithms. Especially in case of solar-energy systems, single-phase connection is often used at low power levels. This can be achieved by using a four-quadrant converter. For optimal reaction to variations of infeed (e.g. by shading by clouds) and grid disturbances, a fast reaction of the control is advantageous. Reaching such properties under the conditions of single-phase grid connection is challenging: The power pulsation and the inability to exchange energy around zero grid voltage require specialized control schemes for dynamic control. This paper presents the control scheme and measurement results for a four-quadrant converter control basing on the `Pole Restraining' concept which allows fast instantaneous-value-based control even for four-quadrant converters connected to a single-phase grid.

Model-based control of converter-connected assets is an option to establish excellent dynamics. Such a control strongly relies on the quality of the model used. In case of power-electronic converters, blanking-time effects introduces a large voltage error, especially at low output voltage. Blanking-time effects depend on the sign (and, to a lesser degree, on the magnitude) of the current flowing in the instant of each single switching event. This can be predicted and compensated by the control - but the effort is high. Also, especially at low current magnitude, the risk of prediction failures grows - and leads to an increase of the voltage error in case of prediction errors. Reducing the risk of miss-prediction requires high modelling effort and/or fast current measurement processed by the main control loop - causing high effort and cost. This paper presents and discusses opportunities and advantages of driver integrated blanking time compensation with low additional effort. A concept for realization is introduced.

Blanking-time (or blocking-time) effects in power-electronic converters have been known since long. They introduce disturbances which are not easily handled by control means. Their compensation is not straightforward, because they depend on the sign (direction) and to a much lesser degree on the magnitude of the current flowing through the switching devices. Depending on the topology of the converter and the relation between blanking time and pulse period, the influence on the output quantities is relevant. This paper analyses blanking-time effects based on measurements performed on a modular multilevel converter - where these effects also influence the harmonic content of the DC voltage considerably. A straightforward FPGA-based compensation mechanism is implemented and its mitigation effect documented.

DC grids offer highly efficient distribution of electric energy, eliminating components and optimizing the use of cables. Efficient generation, however, is still based on AC generators. Power-electronic devices link generators and grid and customize energy flow to the loads. Efficient distribution with low losses demands high voltage, e.g. in the range of 10 kV for ship-size grids. Such voltages challenge power electronics as well as protective devices: Short-circuit protection with fast auto-reclosing in a context where fuses are not applicable has to be solved. This paper proposes modular multilevel converters (MMC) with full-bride (4QC) modules and demonstrates fault mitigation in controlled MMC operation by measurement results. The associated control separates asset characteristic defining the steady-state and transient behaviour and converter-near control operating in the subtransient and transient regime. The feasibility of the approach is demonstrated by selected measurement results.

High-voltage DC (HVDC) transmission lines offer highly efficient transport of electric energy. If applied to comparatively weak grids, self-commutated converters are the proper choice, because they allow stabilizing the grid in case of faults by injecting reactive power. At high voltages of e.g. 400 kV modular multilevel converters (MMC) fulfill all requirements. The first task to master is getting the converters and the grid into operation. For this a two-step pre-charging sequence is needed, because the control of the converter modules of the MMC is supplied from its own DC-link voltages. For testing all relevant aspects of a multiterminal HVDC transmission system a scaled-down test bench has been realized. Four modular multilevel-converters (MMCs) define the multiterminal DC system. With regard to practical demands, no explicit communication between the control systems is allowed for stable operation of the transmission system. This paper gives a short overview of the test bench and then concentrates on the pre-charging of the converters based on AC and DC voltage and demonstrates the powering up of the DC system.

Induction machines are affordable and robust, presenting a valid option for electric vehicles. Many control schemes for such machines are known and have been published. With regard to fast torque dynamics and robustness against parameter variation, stator-flux-oriented control is a very favorable option. This paper presents a stator-flux oriented control which bases on a comprehensive model of the induction machine. A sophisticated compensation of non-ideal converter behavior further enhances the results obtained. These results are documented by measurements and verify excellent performance: Fast response without current overshoot uses the rating of the converter optimally. Dynamic field weakening keeps excellent torque response in the field-weakening range without any voltage margin, too.Fast torque dynamics are not required for fulfilling the commands issued by the driver but for efficient disturbance rejection and additional features like slip-slide control and maximum-traction-point detection. For such features, the underlying torque control defines the performance consequently, fast and precise reaction is requested.