Texture divides an image into subparts called regions. Texture analysis characterizes region using texture content. Local phase quantization is a conventional method, which gives highest classification accuracy. Bilateral filter is also a good approach to obtain smoothness of a digital image while preserving the edges. Also, fast bilateral filter is another approach for high dynamic range images. In this study, new approach is proposed by integrating local phase quantization and fast bilateral filter, which in turn results in good classification accuracy. Using different filter domain parameter and filter range parameter texture, features such as mean, standard deviation, entropy, skewness, and kurtosis are extracted. Finally, for classification, these features are given to k-nearest neighbor (K-NN) classifier. The new hybrid technique is for testing and training images from Brodatz database. The results of proposed technique are compared with conventional local phase quantization results. Best classification accuracy is obtained by hybrid method for different values of domain and range parameters with different window sizes.

Signal processing applications involve in many arithmetic operations. High speed arithmetic operations play an important role in these applications. Multipliers are often considered as the basic building blocks of digital signal processors (DSP). The speed of the multiplier corresponds to DSP. Multiplication is the basic operation to be performed in DSP. In order to implement these multiplications many algorithms are used. In this paper, few algorithms are discussed to implement multiplication. The algorithm discussed in this paper is the most ancient methodology used by Aryans. In this paper reversible Vedic multiplier is proposed using Urdhva Tiryakbhyam (UT) sutra and a comparative study reveals and suggests different logics pertaining to different profile considerations such as power and area.

In order to carry out any arithmetic operation, a basic multiplication operation plays a vital role. Multiplication of any signed (or) unsigned integers can be done using a multiplier. Speed is a major corner in any processing system which in turn depends on the multiplier which acts as a basic building block. There are wide varieties of multiplier architectures that are possible multiplier among them but it cannot perform operations faster. Another possible multiplier is the “Wallace” tree multiplier which can perform operations faster, but it can give fruitful results for unsigned integers. Wallace tree multiplier gives not only speed but also a reduce delay with the help of carry save algorithm and also it uses full adders. Verilog code is simulated and designs are synthesized using Xilinx tool. In this paper, Wallace tree multiplier is compared with conventional multiplier to prove the speed of the Wallace tree multiplier as well the reduced power consumption.

The aim of this paper is to propose the 2-D DWT architecture. The Discrete Wavelet (DWT) is a multiresolution analysis tool with excellent architecture in the time and frequency domains. Previous DWT architectures are mostly based on the modified lifting scheme or the flipping structure. In order to achieve a critical path with only one multiplier, at least four pipelining stages are required for one lifting step, or a large temporal buffer is needed. In this brief, modifications are made to the lifting scheme, and the intermediate results are recombined and stored to reduce the number of pipelining stages. As a result, the number of registers can be reduced to 18 without extending the critical path. In addition, the two-input/two-output parallel scanning architecture is adopted in our design. For a 2-D DWT with the size of N × N, the proposed architecture only requires three registers between the row and column filters as the transposing buffer, and a higher efficiency can be achieved. The implemented architecture represents the simulations in Xilinx for 1-D DWT and 2-D DWT outputs.