Error correcting codes have recently gained more attention due to their applications in quantum resistant cryptography. Their suitability depends on their indistinguishability from random codes. In that sense, the study of the square code of a particular code provides a tool for distinguishing random codes from not random ones. With this motivation, the square codes of some semisimple bilateral group codes, as abelian and dihedral ones, are studied in this paper. For this purpose, bilateral group codes are described as evaluation codes by means of the absolutely irreducible characters of the group. Finally, some results on self-duality and self-orthogonality are recovered under this alternative point of view. (c) 2024 Elsevier Inc. All rights are reserved, including those for text and data mining, AI training, and similar technologies.

Motivated by circular complex interval arithmetic, some operations on closed balls in $\mathbb{C}^n$ are considered. Essentially, the properties of possible multiplications for closed balls in $\mathbb{C}^n$, related either to the Hadamard product of vectors or to the $2$-fold vector cross product when $n \in \{3, 7\}$, are studied. In addition, certain equations involving the defined multiplications are solved.

Nonassociative algebra plays a fundamental role in the description of physical systems. Symmetry is related to the transformations of these algebras, which are controlled by their automorphisms group. Starting from the known structure of finite division rings with 64 elements, we construct some nonassociative finite division algebra of Orders 256 and 512 with a designed automorphism group.

Through a matrix approach of the $2$-fold vector cross product in $\mathbb{R}^3$ and in $\mathbb{R}^7$, some vector cross product differential and difference equations are studied. Either the classical theory or convenient Drazin inverses, of elements belonging to the class of index $1$ matrices, are applied.

Nowadays, multi-processor systems play a critical role in embedded system engineering. As a result, the generation of optimal concurrent implementations is an unavoidable but difficult task. Correct concurrent codes achieving maximum performance on the target platform are hard to obtain. On the one hand, dependencies on concurrent computations, such as shared variables or synchronizations, are extremely difficult to analyze from source code. On the other hand, it is completely unfeasible for designers to manually generate multiple implementations in order to evaluate and compare all the possible design alternatives. To overcome these limitations, this paper presents an automatic code generation approach focusing on communication channel semantics. The approach proposes the use of UML/MARTE models to enable designers to graphically handle dependencies and concurrency of the models. As a result, the automatic generation process enables multiple design alternatives to be easily obtained and evaluated without adding manual effort to the design process. To demonstrate these capabilities, the methodology is tested with two large examples.

The number of cores in embedded systems is continuously growing, supporting increasingly complex concurrent applications. In order to verify that the systems comply specification requirements during the design process, fast simulations and performance analysis tools are required. These simulation frameworks typically use virtualization or host-compiled simulation techniques. On one hand, current host compiler simulators normally offer fast simulations, but they do not exploit host parallelism capacity. On the other hand, some virtual emulation frameworks take advantage of host parallelization, but they do not achieve simulations as fast as native (host-compiled) simulators because of the dynamic binary translation. This paper proposes a parallel host-compiled simulation methodology that aims to make an efficient use of multi-core host platforms. The performance of the proposed technique has been evaluated with the PARSEC benchmark suite [10]. The evaluation also includes comparisons with native execution and other parallel simulation tools. Results demonstrate that the proposed technique reduces simulation time and provide fast estimations of embedded SW code.

One of the first problems that a hardware designer needs to solve when facing a new and complex electronic design, is to know in advance where the critical parts of the design are, and how many resources the design will require. This information will ease the developing of feasible systems and will help in the design of well suited architectures. The Open SVC (Scalable Video Coding) Decoder (OSD) is an open source system created at IETR/INSA at Rennes that implements a SV decoder written in language. The scalable video encoder supposes an important overload compared with its counterpart non-scalable video encoder, which inherently already exhibits a very high computational load. Due to the huge number of functions that form part of the SV video decoder, a set of internal modules that better describes the internal structure of the decoder has been defined. In this scenario, two aspects have been selected to be the critical ones: the computational load and the transaction of data. In order to adopt appropriate decisions related with the system implementation.. This paper presents a methodology based on VIPPE that will be used to perform the profiling of a complex system like the OSD over a user-defined platform, the ZynQ from Xilinx in this case, composed by two ARM cores and an FPGA. The profiling results will guided the implementation of the OSD on the aforementioned ZynQ platform. The methodology can be easily extrapolated to any other complex design.

We use the theory of resultants of polynomials to study the stability of an arbitrary polynomial over a finite field, that is, the property of having all its iterates irreducible. This result partially generalises the quadratic polynomial case described by R. Jones and N. Boston. Moreover, for characteristic three, we show that certain polynomials of degree three are not stable. We also use the Weil bound for multiplicative character sums to estimate the number of stable arbitrary polynomials over finite fields of odd characteristic.

In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to guide and assist the designer in the development process, from UML specifications to implementation and debug on multicore platform. This tool chain will offer the possibility to propose and implement several parallelization strategies and drive the designer into implementation steps. The second objective of the project is to develop monitoring and control techniques in the middleware of the system capable to automatically adapt platform services to applications requirements and therefore reduce power consumption in a transparent manner for applications.

Este trabalho mostra como a Algebra Linear pode contribuir para a discussao da equacao ax = xb em contexto de Algebra Nao Associativa, concretamente em algebras de composicao standard de tipo II associadas a uma algebra de quaternioes e a uma algebra de octonioes. Caracterizam-se ainda algumas solucoes.

The proposed approach presents a method for automatically synthesizing the SW code of complex embedded systems from a model-driven system specification. The solution is oriented to enabling easy exploration and design of different allocations of SW components in heterogeneous platforms, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. The consequent communication overhead reduction can result in an important advantage for system performance optimization.

Model-Driven Engineering (MDE) based on UML is a mature methodology for software development. However, its application to HW/SW embedded system specification and design requires specific features not covered by the language. For this reason, the MARTE profile for Real-Time and Embedded systems was defined. It has proven to be powerful enough to support holistic system modeling under different views. This single-source model is able to capture the required information, enabling the automatic generation of executable and configurable models for fast performance analysis without requiring additional engineering effort. As a result of this performance analysis suitable system architecture can be decided. At this point, the SW stack to be executed by each processing node in the selected heterogeneous platform has to be generated. In the general case this is a tedious and error-prone process with little assistance from available tools. Current practices oblige the SW engineer to develop the code for each node of the heterogeneous multi-core platform by hand. The code has to be written specifically for the selected architecture and architectural mapping, thus reducing reusability. In order to overcome this limitation, the FP7 PHARAON project aims to develop tools able to automatically generate the code to be executed in each node from the initial system model. This affects not only the application code, the static and run-time libraries (e. g. OpenMP/OpenCL), the middleware and communication functions, but also the OS and the driver calls in each node.

Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design alternatives when optimizing system performance. The paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standard UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.

With the increase in the number of processing eleme nts integrated in HW platforms, the development of new solutions helping engineers to design concurrent applications is gaining greater interest. Code refi n ments required to parallelize sequential algorithms are u sually quite complex, and do not guarantee that the decisi ons taken will provide the expected performance result, requiring a costly and iterative design process. To solve this problem, this paper presents a methodology that ena bl s designers to define and automatically create differ ent concurrent architectures for the system, only modif ying different parameters in the UML model. The main ide a is to automatically modify the communication between components, adding to the typical configurable opti ons of performing synchronous, asynchronous or buffered ca lls the idea of enabling parallelization by dividing one se rvice call into several concurrent calls, each one operating w ith part of the data. Examples of use of this idea with vide o applications are presented, demonstrating the perfo rmance improvement obtained in the final system.

Design of embedded systems is facing the challenge of their growing complexity and strict performance requirements. Mod el-driven design solutions are very common in this context, where the UML/MARTE profile is a wellknown solution for real-time, embedded system model ing. During the design process, several specification alternatives can be considered; specifically, the HW/SW platform, concurrent application structure, a pplication allocation into HW/SW platform resources, etc. The exploration of t hese design alternatives enables a set of performance estimations to be obta ined in order to choose the optimal specification, facilitating system implemen tation and minimizing designer effort. The paper proposes an UML/MARTE meth odology the enables automatic estimation of the system to be implemente d. Once the optimal system specification has been defined, the proposed UML/MA RTE methodology enables the final system to be implemented through an automatic synthesis process.

In this text we study the exp–log functors for the categories of uniform groups and uniform Lie algebras.

In this article we study relations between groups and quantum error correcting codes. Groups of central type are used to construct quantum error correcting codes. Both stabilizer and Clifford codes can be derived from a construction involving this kind of groups. A more general construction of Clifford codes will be given and their correcting properties will be examined using group theoretical techniques.

Let p be a prime, G a finite p-group, r the rank of G and e the exponent of G. In this short note we will prove that the exponent of the Schur multiplier of G divides pe+r⌈log2(rlog2p+1p−1)⌉.

In this work we obtain a nontrivial estimate for the size of the set of triples (a,b,c)∈Fq∗×Fq×Fq which correspond to stable quadratic polynomials f(X)=aX2+bX+c over the finite field Fq with q odd. This estimate is an improvement of the bound O(q11/4) conjectured in a recent work of A. Ostafe and I. Shparlinski.

Algebraic methods play an important role in coding theory. For instance, there are many connections between codes and groups. In this paper we will present two results that show different applications of algebraic methods in coding theory. One of them refers to the classical context and another one to the quantum error correcting theory. These results can be found in [5] and [13] respectively, where proofs and more details can be found.