This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures. At first, we consider the generation of compact test sets for designs using onchip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures. We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions.

New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

3D-SOC technology has significant performance and power gains over 2D as interconnects can be shortened significantly. To accrue full benefits of reduced interconnect lengths large designs need to be partitioned into several dies.In this work we propose a hypergraph based multi-objective circuit partitioning scheme for 3D-SOCs that simultaneously reduces the number of inter die connections, which use through silicon vias (TSVs), and reduces additional DFT logic needed for pre-bond test of dies. An Ordered Block hypergraph partitioning scheme is proposed to achieve these objectives. Experimental results on several industrial circuits demonstrate the effectiveness of the proposed approach.

Through silicon vias (TSVs) have a significant impact on the area and timing performance of a 3D-SOC. Performance aware design partitioning is required to reduce delay by placing gates on critical paths close to each other on the same or adjacent dies in the 3D-SOC. Also, pre-bond test of dies in the 3D-SOC is required to insure correct functionality of the dies before bonding. Additional design for test (DFT) logic for pre-bond test also depends on the design partitions used. In this work we propose a hypergraph based multi-objective netlist partitioning scheme to improve timing performance of 3D-SOC while keeping additional DFT cost low. Accurate interconnect estimation models are incorporated during partitioning to reduce delay and interconnect length variations across dies. Results on ISCAS89 and ITC99 benchmark circuits demonstrate the improved timing performance and reduced DFT cost using the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix crosstalk violations in the clock tree by making minimal design changes and maintaining skew bounds. We propose a novel approach for making engineering change order (ECO) changes in the clock network to remove crosstalk violations. A two-pronged approach based on wire-translocation and rerouting is presented. Wire translocation, i.e., changing the track for a net to another free track with less crosstalk, eliminates a large percentage of removable violations. A linear time procedure to check if a violation is removable by translocation is developed. Next, an efficient rerouting method based on an incremental loci-finding algorithm is combined with linear time dynamic programming approach to eliminate the remaining crosstalk violations. Simulation results for randomly-generated clock tree of different sizes and benchmark circuits demonstrate the effectiveness of this approach

Weighted random testing is gaining popularity as an economical method for external as well as for built-in-self-testing (BIST). In weighted testing we have to satisfy two competing requirements: to keep both the test length and the hardware cost low. Usually multiple sets of weights are required. To reduce their number and, as a consequence, the hardware cost, we quantize the weights to values which can be easily generated in hardware. The concept of weight quantization, its theory and its application to reducing the number of weight sets to be implemented in hardware, are studied. When weighted test patterns are generated it is likely that the fault coverage of the corresponding test sets thus obtained overlap. To compensate for this we apply the weight sets selectively in reverse order, thereby reducing the test length and the hardware cost. We develop a new method of weight generation, adaptive weight generation, which applies our methods of selective reverse simulation and weight quantization; in this way, both the test lengths and the number of weight sets are reduced. Simulation experiments indicate that significant improvements, both in terms of time and hardware cost, are afforded by our technique