Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system complexity and minimize data throughput requirements in positron emission tomography (PET) applications. The TDCs have an average LSB of 53.5 ps. The ANN is fully reconfigurable, the user being able to change its topology as desired within a set of constraints. The chip can execute 363 MOPS with a maximum power consumption of 1.9 mW, for an efficiency of 190 GOPS/W. The system performance was tested in a coincidence measurement setup interfacing Smarty with two groups of five 4 mm × 4 mm analog silicon photomultipliers (A-SiPMs) used as inputs for the TDCs. The ANN succesfully distinguished between six different positions of a radioactive source placed between the two photodetector arrays by solely using the TDC timestamps.

Blumino is the first analog silicon photomultiplier with integrated amplifier, comparator and time-to-digital converter (TDC). The combination of a photodetector together with on-chip readout circuitry enables system-level advantages, such as internal parasitic reduction, compactness and simplicity. The analog silicon photomultiplier has a third output, called fast terminal (FT), in addition to the anode and cathode, which is used for timing measurements. The analog silicon photomultiplier presents excellent photon detection efficiency greater than 40% at 420 nm, making it suitable for positron-emission tomography. Measurement results of the TDC indicate a resolution of 128 ps least significant bit (LSB) with a differential nonlinearity and integral nonlinearity of -1/+5 LSB and -2.4/+0.9 LSB, respectively. The discriminator comprises two preamplifier stages followed by a complementary self-biased differential amplifier stage which is coupled to the analog silicon photomultiplier's FT through a decoupling capacitor. The sensor is also fully backward-compatible through the standard output which can be coupled to dedicated ASICs and standard readout integrated circuits. In addition to the electrical, radiation, and optical performance, the integration of a custom CMOS analog silicon photomultiplier process with standard CMOS process was investigated.

We discuss the architecture and characterization of an advanced frontside-illuminated (FSI) multi-channel digital silicon photomultiplier (MD-SiPM) fabricated in 0.18 µm/0.18 µm 3D-stacked CMOS technology. The top-tier chip houses FSI photodetectors, the bottom-tier chip photon timestamping, signal processing, and communication logic. The total chip size is 7.5×4.2 mm2, comprising two arrays of 8×8 clusters, each composed of 64 single-photon avalanche diodes (SPADs). The sensor was electro-optically tested using a laser-based setup. Key parameters, such as dark count rate, hot pixel distribution, TSV yield, response linearity and saturation were characterized and complemented by preliminary radiation measurements on LYSO scintillators coupled to a 22Na source.

15:18 R02 A 40/22nm 200MP Stacked CMOS Image Sensor with 0.61um Pixel Masayuki Uchiyama2, Geunsook Park1; Tomoyasu Tate1, Masashi Minagawa2, Shino Shimoyamada2, Zhiqiang Lin1, King Yeung1, Lien Tu1, Wu-Zang Yang3, Alan Hsiung1, Vincent Venezia1, Lindsay Grant1 1 OmniVision Technologies, Santa Clara, CA, USA 2 OmniVision Technologies Japan, Kanagawa, Japan 3 OmniVision Technologies Taiwan, Hsinchu, Taiwan 5

We present a frontside-illuminated (FSI) multichannel digital silicon photomultiplier (MD-SiPM) fabricated in 0.18 μm/0.18 μm 3D-stacked CMOS technology. The top tier is dedicated to the FSI photodetectors, while the bottom tier comprises timestamping, processing, and communication electronics. The MD-SiPM is segmented in two arrays of 8×8 clusters of 64 single-photon avalanche diode (SPAD) pixels each. A dedicated time-to-digital converter (TDC) is included within each cluster. The pixel pitch is 50 μm, the fill factor 67%, and the peak PDE 35% at 500 nm. The TDC is triggered by the first firing SPAD, and its identification code or address is propagated and stored by a winner-take-all architecture. The 128+1 TDCs, which are based on a multi-path gated ring oscillator, exhibit an LSB of 8 ps and a single-shot resolution of 50 ps (RMS) as determined through initial measurements on an independent structure. The power consumption per TDC is below 1.8 mW. The data is validated and read out from the clusters through an on-chip scheduling controller, while a random-access architecture enables access of each cluster individually. Preliminary characterization demonstrates the suitability of the system for the target application.

The coincidence time resolution (CTR) of a time-of-flight positron emission tomography (TOF-PET) scanner is an essential parameter, which determines signal-to-noise ratio (SNR) in image reconstruction algorithms. CTR has an important impact on scintillation-based detectors used in TOF-PET. Cherenkov PET has emerged as a prompt-photon based radiation detector, which has more accurate light-photon emission statistics. However, light transport becomes a dominant degradation effect in the light-photon detection statistics, which is highly correlated to the crystal length and consequently to the gamma-photon detection efficiency. This work focuses on finding the optimal design in terms of timing resolution and gamma-photon detection efficiency for Cherenkov detectors. Radiator design considerations such as size, materials and coatings, along with electronic jitter, and dark count rate (DCR), are included in a mathematical simulation that determines their effect on timing resolution. Currently, two different scintillators were simulated, namely PbF2 and PbWO4, with a maximum Cherenkov count per frame of 12 photons; an electronic jitter of 4.3ps to 42.5ps (standard deviation) was added. Simulation results confirm the high impact of jitter on the uncertainty of arrival times of Cherenkov photons.

In this work, we present a complete design implementation and characterization of an analog silicon photomultiplier (SiPM) with integrated time-to-digital converter (TDC).The combination of a photodetector together with on-chip readout circuitry in close proximity enables system-level advantages such as internal parasitic reduction for better singlephoton timing resolution (SPTR), but also overall simplicity and compactness.The system comprises a C-Series analog SiPM developed by SensL, a TDC, and a comparator.The design was implemented in 0.35µm CMOS technology.The proposed analog SiPM features 48% photon detection efficiency (PDE) at 420nm wavelength and +6.0V excess bias.Thanks to the small size of the electronics, the overall sensor fill factor is 75% and its sensitive area is 3×3mm 2 .The SiPM fast output, which is a specialized terminal for fast timing output signals, has a parasitic capacitance of about 12pF.The TDC is a multi-path-gated ring oscillator with a 6-bit coarse counter and 9-bit phase detector.Post-layout simulation results indicate a 65ps LSB in typical corner with differential non-linearity (DNL) and integral non-linearity (INL) of ±0.55LSB and ±1LSB, respectively.The comparator is composed of two preamplifier stages followed by a complementary self-biased differential amplifier stage (CSDA), directly coupled to the fast output through a capacitor.Post-layout simulation indicates 48V/ns slew rate and a preamplifier stage bandwidth of ~1GHz.The comparator power consumption without the additional preamplifier stage is 198µW.

We present a design that implements digitization of an analog SiPM's fast output on chip to pave the way to higher granularity in the digital conversion of photon detection. The design comprises a comparator bank, time-to-digital converters (TDCs), and electronics for interfacing with the external world. The TDC is a multipath, gated ring oscillator with a counter and phase detector, implemented in 0.35μm CMOS technology. Simulation results indicate a DNL of ±0.55LSB and an INL of ±1LSB, a large, adjustable range, and a typical resolution of 65ps (LSB).

The thesis presents a design that implements digitization of an analog SiPM's fast output on chip realized in order to minimize the complexity and increase the photon detection granularity. The design comprises a time-to-digital converter (TDC) in 0.35um CMOS technology. The TDC is a multi-path gated ring oscillator with a 6 bit counter for coarse bits and 9 phase detectors for the fine bits. Schematic and post-layout simulations indicated a 65ps LSB in the typical corner with a DNL of +/-0.55LSB and an INL of +/-1LSB. The TDC design does not comprise any additional calibration circuitry.