We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.
Zhaokai Liu合作论文数Univ Calif Berkeley, Berkeley, CA 94720 USA1
Zhongkai Wang合作论文数Univ Calif Berkeley, Berkeley, CA 94720 USA1
John Wright合作论文数Univ Calif Berkeley, Berkeley, CA 94720 USA1
Sijun Du合作论文数Department of Microelectronics, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology1
Minsoo Choi合作论文数1
Elad Alon合作论文数Department of Electrical Engineering and Computer Sciences, University of California, Berkeley;Berkeley Wireless Research Center, University of California, Berkeley1
Eric I-Chao Chang (張益肇)合作论文数AI + Health Startups1
Woorham Bae合作论文数1
Borivoje Nikolic合作论文数Department of Electrical Engineering and Computer Sciences, University of California at Berkeley;Berkeley Wireless Research Center, University of California at Berkeley1
Nathan Narevsky合作论文数1
Colin T. A. Schmidt合作论文数1
