Large-area and dense arrays of nanometric scale structures are commonly fabricated for several applications. The characterisation of sub-micron structures (below 1 mu m) at a large scale as well as the related data analysis are challenging tasks. Here, we present a method to address the image acquisition, the data extraction and the data analysis, applied to the evaluation of the uniformity of nanometric structures in a silicon master. Automated routines for both high and low magnification Scanning Electron Microscope (SEM) imaging have been successfully developed. SEM images have been automatically acquired by scripting routines, which collect large amounts of images of the nanometric structures covering multiple regions of the wafer in a few hours. Geometric parameters of the nanometric structures such as diameter, period and height have been extracted from the raw images using the developed image processing scripts. Finally, the data extracted from more than 4800 images acquired with three different characterisation scripts (1600 images for each study) have been analysed and plotted according to their position in the wafer.

Spintronic nanodevices are consolidating a highly reputed position in advanced manufacturing industry, not only due to progresses in magnetic hard disk sensors, but also the memory market. The ability to integrate magnetic thin films on large area wafers and subsequent nanofabrication into functional devices is key for such success. This work describes methodologies used for definition of sub-100 nm pillars, using reliable via opening to contact nanopillars buried in a dielectric film. A two consecutive step electron beam lithography process is used to fabricate current-perpendicular-to plane nanodevices. The first step is required to pattern nanopillars down to 30 nm. The second provides access to nanopillar top through nanovias definition and reactive ion etching. Optimum alignment of multilevel exposures ensures the most accurate positioning in the shortest time. Most importantly, the results are obtained on 150 mm diameter wafers, where additional challenges of uniformity of resists, oxides and metals are critical for end-point control and improved yield of fabricated devices. The design of customized test structures allowed control of etching end-point. (C) 2018 The Society of Manufacturing Engineers. Published by Elsevier Ltd. All rights reserved.