We describe the electron-to-image signal chain and performance of a high-speed, large format (4096 x 4096), 8μm pitch, event-based, direct electron CMOS imager for cryogenic electron microscopy (cryo-EM) applications. The distinguishing elements in this signal chain are: use of current-mode circuits instead of voltage-mode to avoid settling lag, and on-chip event detection combined with sparse readout to minimize the irrelevant information transferred per frame. This resulting image sensor can operate at an exposure rate approx. 8x the current nearest competing camera while maintaining high detection efficiency and low noise at high speed; specifically, the sensor exceeds 2500fps in “brute force” readout mode and 8000fps in “event-based sparse” readout mode, and is currently the fastest 4k sensor for cryoEM application. The detailed sensor architecture, event based sparse algorithm and its implementations were previously discussed in [1,2,3]; its stitching configuration, the chip photograph, and the 4T radiation hard pixel layout are shown in Figure 1(a-c).

Objective. Decoding neural activity has been limited by the lack of tools available to record from large numbers of neurons across multiple cortical regions simultaneously with high temporal fidelity. To this end, we developed the Argo system to record cortical neural activity at high data rates. Approach. Here we demonstrate a massively parallel neural recording system based on platinum-iridium microwire electrode arrays bonded to a CMOS voltage amplifier array. The Argo system is the highest channel count in vivo neural recording system, supporting simultaneous recording from 65 536 channels, sampled at 32 kHz and 12-bit resolution. This system was designed for cortical recordings, compatible with both penetrating and surface microelectrodes. Main results. We validated this system through initial bench testing to determine specific gain and noise characteristics of bonded microwires, followed by in-vivo experiments in both rat and sheep cortex. We recorded spiking activity from 791 neurons in rats and surface local field potential activity from over 30 000 channels in sheep. Significance. These are the largest channel count microwire-based recordings in both rat and sheep. While currently adapted for head-fixed recording, the microwire-CMOS architecture is well suited for clinical translation. Thus, this demonstration helps pave the way for a future high data rate intracortical implant.

Here we demonstrate the Argo System, a massively parallel neural recording system based on platinum-iridium microwire electrode arrays bonded to a CMOS voltage amplifier array. The Argo system is the highest channel count in vivo neural recording system built to date, supporting simultaneous recording from 65,536 channels, sampled at over 32 kHz and 12-bit resolution. This system is designed for cortical recordings, compatible with both penetrating and surface microelectrodes. We have validated this system by recording spiking activity from 791 neurons in rats and cortical surface Local Field Potential (LFP) activity from over 30,000 channels in sheep. While currently adapted for head-fixed recording, the microwire-CMOS architecture is well suited for clinical translation. Thus, this demonstration helps pave the way for a future high data rate intracortical implant.### Competing Interest StatementK.S., A.A.K., A.P.S., T.M.S, Y.N., A.T., P.O., C.L., D.P., K.N., K.M.B., S.S., M.S.H., B.K., M-E.S.H., R.J.E., I.M., D.F., A.M.S., V.G., Y.K., M.S., H.S.S., M.R.A. are current or former compensated employees or consultants of Paradromics, Inc., a brain-computer interface company. P.G., A.B-F, S.V., A.V.K, B.L., B.D. are compensated employees or consultants of Caeleste, CVBA, a circuit design company.

Introduction Series of binarized images can be used to construct low/no noise, high dynamic range images at high (>1000fps) frame rates. This approach is a benefit to applications such as scientific, medical and SPAD or QIS [3,4,5] sensors where speed is needed to avoid multiple hits on the same pixel in a single frame, especially for large array sizes. In this paper, a large format (36.1x40.2 mm), 4k x 4k CMOS binarized image sensor is presented. To further increase the frame rate in case of sparse imaging (which is often the case, especially with higher frame rate), on-chip data reduction has been implemented. Frame rates up to 8000fps can be reached where only the pixel kernels with hits, and their corresponding addresses are read out; otherwise, in brute force mode where all pixels are read out, the frame rate reaches 2800fps. This sensor is an evolution of [1] with increased pixel count, modified sparse readout algorithm, optimized priority encoder, optimized sense amplifier (1-bit ADC) and high speed digital IOs.

Introduction In this paper we present an image sensor with a very high linear dynamic range that is obtained by combining a pixel with using three level transfer gate method and a column-level automatic gain selection. The automatic gain selection (AGS) picks one out of three linear ranges each having a largely different conversion gain. The data rate remains the same as without high dynamic range, thus preserving the maximal frame rate.

Introduction In this paper we compare 4 different methods of HDR imaging that have linear response, PSN limited operation at all light levels, true CDS, and are ca pable of performing synchronous shutter operation. This narrow definition excludes many existing alternativ e “HDR” methods [1], which fail in one of these spe cs. Logarithmic response[4], lin-log[5] and multiple sl ope methods [3] fail because of not being linear or n t having a single synchronous integration time. Meth ods based on varying the integration time or using multiple different size photodiodes fail at having PSN limited operation and methods based on acquirin g and combining multiple frames at different gains fail t o operate in synchronous shutter mode.

The silicon-on-insulator (SOI) platform allows to make ultra-compact photonic integrated circuits by means of standard processes used for silicon CMOS. Basic properties of SOI waveguides and the coupling to fiber are briefly discussed. Afterwards, various WDM-components (filters and demultiplexers) based on high-contrast nanophotonic waveguides in SOI are reported.

Silicon-on-insulator is rapidly emerging as a versatile platform for a variety of integrated nano-photonic components. This paper discusses the variety of merits offered by this system. The key technological challenges are discussed as well as the potential in multiple application fields.

A rigorous analysis and design of efficient coupling from photonic crystal (PhC) waveguides into conventional dielectric waveguides is reported. Closed-form expressions for the reflection and transmission matrices that completely characterize the scattering that occurs at the interface are derived based on an eigenmode expansion technique and a Bloch basis. Analytic expressions are used to analyze the reflection into PhC waveguides. We obtain that negligible reflection can be achieved by choosing a certain interface within a PhC unit cell. Furthermore, analytic expressions are used to design a novel and compact coupler structure in order to achieve high coupling efficiency when broad dielectric waveguides are considered. Thereby, transmission efficiencies near 100 from the fundamental guided Bloch mode into the fundamental waveguide mode are achieved.

Nanophotonics promise a dramatic scale reduction compared to contemporary photonic components. This allows the integration of many functions onto a chip. Silicon-on-insulator (SOI) is an ideal material for nanophotonics. It consists of a thin layer of silicon on top of an oxide buffer. In combination with high-resolution lithography, one can define a high refractive index contrast both in horizontally and vertically, resulting in a tight confinement of light. Moreover, SOI can be processed with industrial tools now used for silicon microelectronics. There are two candidates for nanophotonic waveguides. Photonic wires are basically conventional waveguides with reduced dimensions and a high refractive index contrast. These waveguides with submicron dimensions can have bend radii of only a few micrometres. The alternative is to use photonic crystals, which confine light by the photonic band gap effect. Introducing defects in a photonic crystal creates waveguides and other functional components. To make nanophotonics commercially viably, mass-manufacturing technology is needed. While e-beam lithography delivers the required accuracy for nanophotonic structures, it is too slow. We have used deep-UV lithography, used for advanced CMOS fabrication, to make nanophotonic waveguides. The fabrication quality is very good, which translates to low propagation losses. E.g. a 500nm (single-mode) photonic wire has a propagation loss of only 0.24dB/mm. Using these low-loss waveguides, we have implemented a variety of nanophotonic components, including ring resonators and arrayed waveguide gratings.

We report. taper designs with high transmission efficiencies and With lengths shorter than those needed for. adiabatic operation., The tapering, occurs between rectangular optical waveguides with the same vertical silicon-on-insulator layer structure, but with different horizontal Widths, namely 0.5 and 2.0 mu m, and for taper length s between 0.5 and 3.0 mu m. After a comparison between two different optimization methods in a two-dimensional calculation scheme, one of these is repeated using three-dimensional calculations. The results show that, also in the length region where conventional linear and parabolic tapers are not yet adiabatic, tapers with a high efficiency can be designed by applying complex taper structures with. more degrees of freedom.

We present a compact planar coupler connecting two optical waveguides with highly different widths. The coupler consists of various nonperiodic waveguide sections, whose dimensions are determined using a genetic optimization algorithm. Efficiencies that exceed those of the more conventional designs with similar lengths, like gradual linear tapers, were obtained in silicon-on-insulator using 248-nm-deep ultraviolet lithography.

For the compact integration of photonic circuits, wavelength-scale structures with a high index contrast are a key requirement. We developed a fabrication process for these nanophotonic structures in Silicon-on-insulator using CMOS processing techniques based on deep UV lithography. We have fabricated both photonic wires and photonic crystal waveguides and show that, with the same fabrication technique, photonic wires have much less propagation loss than photonic crystal waveguides. Measurements show losses of 0.24dB/mm for photonic wires, and 7.5dB/mm for photonic crystal waveguides. To tackle the coupling to fiber, we studied and fabricated vertical fiber couplers with coupling efficiencies of over 21%. In addition, we demonstrate integrated compact spot-size converters with a mode-to-mode coupling efficiency of over 70%.

We present a detailed analysis of butt coupling from conventional dielectric waveguides into photonic crystal waveguides. Closed-form expressions for the reflection and transmission matrices based on an eigenmode expansion technique are derived and validated by means of simulations. We use them to investigate butt-coupling losses in two kinds of photonic crystal structures: one formed by rods with a higher refractive index than the surrounding medium and the other formed by air holes inserted in a high-refractive-index medium. The origin and difference of coupling losses between the two photonic crystal structures is analyzed and discussed. We show that, although the coupling efficiency is much worse in the former structure, it can be significantly improved by choosing the optimum interface position that minimizes the mode impedance mismatch. Furthermore, the dependence of coupling efficiency on frequency is also analyzed. Finally, we also relate some traditionally used approximate formulas to our rigorous expressions.

The silicon-on-insulator (SOI) platform allows to make ultra-compact photonic circuits by means of standard processes used for advanced CMOS. Various WDM-components (filters and demultiplexers) based on high-contrast nanophotonic waveguides in SOI are reported.