Undesired resonances on high-speed differential signals are studied in this paper, which is caused by the adjacent narrow ground line without stitching vias. Due to space limitations in the high-speed channel layouts of certain package applications, the ground (GND) line is often narrow and has insufficient stitching vias, potentially causing undesired resonance in high-speed differential signals. In this study, these undesired resonances were investigated using 3D simulations, revealing that they can be modeled as parallel-coupled half-wavelength resonance. The resonance frequency of the parallel-coupled half-wavelength resonance structure can be predicted well using the formula based on the GND line length. Moreover, three potential solutions to undesired resonance are proposed, providing a practical guide for GND line routing in specific applications.

To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for the calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry-induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, physical explanation, and various design cases are presented for validation.

Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.

Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heatsink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction methods are validated with different buffer types, including low-voltage differential signal, high-speed current steering logic, low-voltage positive emitter-coupled logic, and low-voltage complementary metal–oxide–semiconductor, in a device under test with the given design.

The performance of the high-speed links in the electronic system is highly dependent on the quality of the clock signal, which can be quantified by phase noise. The phase noise represents the instabilities of the signal in the frequency domain by measuring the power at various offsets from the carrier frequency. The root cause for the phase noise of the clock output at the resonance frequency is analyzed and identified in this paper. The power supply, the heat sink, and the external crystal are the main sources of the phase noise. Spurious occurs at the frequency of the power rail in the measured phase noise. The heat sink over the chip induces the conductive coupling noise to the clock. The low-frequency bump in the phase noise plot turns out to be induced by the external crystal design of the clock. More attention should be paid to the ground routing of the external crystal to ensure the quality of the clock output.

2 N -port de-embedding has been well studied previously by using the higher order modal-based S-parameters. Such idea is successfully validated by using the 2X-Thru de-embedding, as well as the classic TRL. Non-2 N even number (such as 6, 10, 12, etc.) port network S-parameters de-embedding is derived and validated in this paper. By inserting a factitious single-ended 2X-Thru before the fixture characterization, the derivation and validation are demonstrated through a 6-port 2X-Thru de-embedding example. After the fixture characterization, the inserted artificially single-ended 2X-Thru will be removed before the step of fixture removing calculation. As the 2X-Thru de-embedding application always has even number of port 2X-Thru fixtures, the idea in this paper extend the 2X-Thru de-embedding to any arbitrary number of port. The derivation and justification are also suitable for other de-embedding algorithms with even number of port.

Because of the simplicity of design and measurement, as well as the accuracy of results, the 2x-thru de-embedding has replaced the traditional de-embedding algorithms such as thru-reflect- line and short-open-load-thru for printed circuit board (PCB) characterization. In this paper, the theory of 2(n)-port 2x-Thru de-embedding is derived first. The self-error reduction schemes are introduced to mitigate the de-embedding errors due to non-ideal manufacturing effects that make mode conversion terms non-zero. Both the theory and the self-error reduction schemes are fully validated through simulation and measurement cases.

The mobile industry processor interface (MIPI) standards defines industry specification for design of mobile devices such as smartphone, tables, laptop and hybrid devices. Such standard plays a critical role in the Internet of Things (IoT), 5G mobile devices, as well as autopilot automobiles. MIPI specification has comprehensive requirements on the data storage, data transfer, display, camera, memory, power, etc on the transmitter and receiver. In the testing phase, the transmitter and receiver may not be easily directly measured. Herein, a fast transmitter and receiver eye diagrams calculation methodology is necessary to predict the RX and TX performances of those devices. The calculated RX and TX eye diagrams are evaluated by using the D-PHY protocol to identify the quality of the signals. An in-house MIPI tool is built to directly display the calculated eye diagrams as well as the MIPI D-PHY report in the PC. The validations are performed by using both simulation and measurement examples.

Crosstalk noise on the printed circuit board is usually decreased by adding shielding ground (GND). In the trace routing area, the shielding vias are added to isolate the coupling between different traces. In the ball gate array (BGA) and pin field area, assigning more GND pins has demonstrated the effectiveness of crosstalk reduction between signals. However, such design decreases the signal to ground (S:G) ratio dramatically, herein, it is not suitable for applications that require high signal pin density. Unlike the treatment in the conventional methodology, in this paper, the differential crosstalk is mitigated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field regions. New full pin map patterns are proposed and compared with the conventional full pin map patterns. Without sacrificing the S: G ratio, the proposed maps prove the superiority in mitigating both differential far-end and near-end integrated crosstalk noise. To maintain the low crosstalk level in the entire link path, guidance of differential trace routing is provided and demonstrated in the details. All models in this paper satisfy SerDes channel designing and manufacturing requirements.

In this study, the structure that a stripline crosses with a narrow slot on the adjacent ground plane was rigorously studied in both a signal integrity and an electromagnetic interference point of view. A partial-element equivalent-circuit (PEEC) based circuit model was proposed to analyze the local region close to the slot, and it can be connected to the plane model and the transmission line model later. Based on an equivalent principal, the problem under a study can be converted to a mixed coupling problem between electrical surface current at the stripline and magnetic surface current on the slot. Therefore, the structure under the study can be treated as a complete cavity surrounded by the perfect electrical conductor at the top and bottom surfaces and a perfect magnetic conductor at four sides, so that the cavity Green's functions can be used in the PEEC formulation. The results obtained by the proposed method matched well with those obtained by a finite-element-based commercial tool.

Because of the simplicity of design and measurement, as well as the accuracy of results, the 2×-thru de-embedding has replaced the traditional de-embedding algorithms such as thru-reflect-line and short-open-load-thru for printed circuit board (PCB) characterization. In this paper, the theory of [$2^{n}$-port 2×-Thru de-embedding is derived first. The self-error reduction schemes are introduced to mitigate the de-embedding errors due to non-ideal manufacturing effects that make mode conversion terms non-zero. Both the theory and the self-error reduction schemes are fully validated through simulation and measurement cases.

A modal approach for parallel plate impedance and equivalent inductance extraction for power integrity analysis including ball grid arrays (BGAs) between two parallel plates is presented. Since the BGAs are placed close to each other, the current flowing through each ball is not uniformly distributed due to the proximity effect. In this paper, a modal-based cavity method is proposed to count for this proximity effect. Analytical solutions for both the parallel plate impedance and the equivalent inductances associated with the BGAs are derived from the modal-based cavity method. The proposed method is validated by finite element method simulations and the application of the proposed method for power distribution network design is demonstrated.

Material properties of dielectric substrates play an important role in high-speed printed circuit board (PCB) design. The Transmission Line-Based material property extraction method is an effective way to obtain substrate properties. However, the method requires transmission line dominated Sparameter data. Even with de-embedding, S-parameters may include non-transmission line effects. Thus, to obtain correct material properties, it is necessary to truncate the S-parameter data at a frequency before non-transmission line effects begin to dominate. In this paper, a novel binary fitting-based method is proposed to find the truncation frequency accurately and efficiently. By using a binary search algorithm and physics-based fitting method, the proposed method is able to find the truncation frequency in only a few iterations. This method has been validated for hundreds of real measurement cases and has shown good adaptability and rationality.

Dielectric substrate properties are critical for highspeed circuit design. It is important to accurately characterize material's dielectric constant (DK) and dissipation factor (DF) after multi-layer PCB fabrication. A method using measured S-parameters and stripline cross-section geometry information to extract DF is developed. Unknown contribution of foil surface roughness to the transmission line loss is reduced by taking into account the ratio between the differential and common mode resistances (K). DF is extracted by relating it to the modal attenuation factors, PUL inductances and capacitances, and K. Several examples are provided using full-wave simulation and fabricated PCB, which demonstrate feasibility of the proposed method.

The integrated crosstalk noise (ICN) has been widely used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, the differential ICN mitigation scheme by using idea of orthogonality is implemented in two adjacent differential pairs first. In the full pin map area of SerDes channel, new pin map patterns based on such scheme are prosed and compared with the conventional pan map patterns. The new pin maps mitigate the differential ICN drastically, yet maintain the G:s ratio. A preliminary study is conducted on fan-out trace routing to maintain the benefit from new pin map patterns.

The procedures of lX-Reflect Smart Fixture De-embedding (SFD), 1-Port Auto Fixture Removal (AFR), and 2X-Thru SFD are compared from various perspectives: test fixture design, the de-embedding procedure, and the de-embedded results. The accuracy of the fixture characterization and de-embedded result is the key figure of merit (FOM) in each de-embedding method. Full-wave models were built to evaluate the FOM of these three methods, by comparing the scattering parameters (S-parameters) and TDR. A test coupon for measuring the USB-C cables is adopted to serve as manufactured validation purpose.

The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1]. A p topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz.

Compared to 4-port de-embedding, 8-port de-embedding is much more challenging due to the presence of crosstalk terms in both the differential mode and the common mode. Using the 2nd order mixed-mode concept, this work proposes an 8-port smart fixture de-embedding (SFD) method. The proposed method neglects modal conversion terms by requiring balanced and symmetrical designs. Analysis showed that this approximation generally has negligible impact on the de-embedded differential results with careful test fixture design.

In this paper, two different micro probes (D-probe and GSSG probe) are studied. A specially designed PCB was used to compare the electrical performances of DUTs with de-embedded fixtures for the micro probes and 2.9 mm connectors. Smart Fixture De-embedding (SFD) was used to de-embed the S-parameters of the DUT from the test fixtures. The results showed consistent results of DUTs using both micro probes and 2.92 mm connectors up to nearly 40GHz.

The integrated crosstalk noise (ICN) has been wildly used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, a differential ICN analysis is performed for several configurations of package-to-PCB transitions. Using the design of experiment (DoE) statistical method, differential ICN is quickly estimated for various input factors such as pin mapping, physical dimensions, and level of shielding. Optimization guide line is proposed to maintain the tradeoff among the differential ICN, design space, and manufacturing cost.