The grown-in dislocation dynamics and interaction mechanisms with growth twins are investigated in-situ during the directional solidification of silicon crystal. The melting, solidification and cooling down process is performed in a dedicated installation at the European synchrotron radiation facility and is followed by X-ray Bragg diffraction imaging techniques (X-ray topography) at the mesoscale in real-time. Existing dislocations in the seed are observed to propagate in the up-grown crystal via replicas. They expand vertically with the moving solid-liquid interface being always aligned perpendicular to the growth front. During the solidification process when they meet a growth twin lamella (Σ3{111}), they neither pile-up nor transmit through the boundary. They are blocked by the twin, but they continue to move laterally behind the growth front due to the thermomechanical stresses in the system. The existence of dislocations at the solid-liquid interface, their evolution and interaction with twin boundaries is discussed, as growth proceeds, based on a detailed crystallographic analysis of the system.

Succeeding with ultrathin silicon wafer sawing by diamond multi-wire saw, is not only a matter of optimization; the challenges of thin wafer production and the capability limit have not yet been fully understood. In this work, we have seen that regular pairing of wires occurs when the wire-wire separation distance is reduced below some critical value. The wire pairing leads to wire jumps on the wire guide rolls, and if the run is not stopped, it leads to wire breakage. Moreover, it effectively obstructs the production of wafers thinner than the critical wire-wire distance.We suggest that the physical explanation to the observed limitations to ultrathin wafer sawing, by diamond multi-wire saw, is related to the capillary force acting on the wires due to the sawing liquid bridge connecting the wires. The hypothesis is supported by simplified mathematical modelling including capillary and spring forces between infinitely long, parallel wires. The calculations suggest that capillary forces are the main reason for wire pairing, and that wire pairing will occur when the wire distance is below some critical distance. This matches the observed, experimental behavior. The critical distance will vary with wafer saw design and operation.To succeed with cutting very thin wafers, we recommend using lower surface tension sawing fluid or even dry in-cut, to reduce the capillary forces and thus decrease the critical wire separation distance, and to reduce wire oscillations to decrease the probability of sub-critical wire-wire separation distance. To reduce the vibration amplitude, shorter distance between the wire guide rolls, thinner wires, and increased wire tension are suggested.

The growth of multicrystalline silicon and the formation of a random angle grain boundary, as well as the dislocation generation and expansion is observed dynamically in situ, by Synchrotron X-ray imaging techniques. The focus is kept on a random angle grain boundary since its behavior is particularly important to better understand the HP mc-Si (High Performance Multi-crystalline Silicon) photovoltaic properties. Due to the process conditions and to the grain competition that occurs during the solidification, a facetted {111}/facetted {111} groove is formed by this random angle grain boundary at the solid/liquid interface. It is shown how the shape of the solid/liquid interface allows the change of the preferential {111} growth facet and affects the grain boundary propagation direction. In one of the groove configurations, the two adjacent {111} facets do not have the same growth velocity and as a consequence the corresponding grain boundary does not follow the bisector of the angle between the two facets. Indeed, the direction of the grain boundary is determined by the growth velocities of the facets which control the grain competition. Moreover, under these experimental conditions a clear relationship is observed between the existence of random angle grain boundaries and the local generation of dislocations as well as their expansion. By comparison, dislocation emission is not observed at the level of Σ3 {111} grain boundaries.

Wafers from three heights and two different lateral positions (corner and centre) of four industrial multicrystalline silicon ingots were analysed with respect to their grain structure and dislocation density. Three of the ingots were non-seeded and one ingot was seeded. It was found that there is a strong correlation between the ratio of the densities of (coincidence site lattice) CSL grain boundaries and high angle grain boundaries in the bottom of a block and the dislocation cluster density higher in the block. In general, the seeded blocks, both the corner and centre block, have a lower dislocation cluster density than in the non-seeded blocks, which displayed a large variation. The density of the random angle boundaries in the corner blocks of the non-seeded ingots was similar to the density in the seeded ingots, while the density in the centre blocks was lower. However, the density of CSL boundaries was higher in all the non-seeded than in the seeded ingots. It appears that both of these grain boundary densities influence the presence of dislocation clusters, and we propose they act as dislocation sinks and sources, respectively. The ability to generate small grain size material without seeding appears to be correlated to the morphology of the coating, which is generally rougher in the corner positions than in the middle. Furthermore, the density of twins and CSL boundaries depends on the growth mode during initial growth and thus on the degree of supercooling. Controlling both these properties is important in order to be able to successfully produce uniform quality high-performance multicrystalline silicon by the advantageous non-seeding method.

A p-type Cz-Si crystal has been pulled with varying pulling speed in order to produce wafers containing two distinct regions; A region with silicon self-interstitial defects, and a vacancy dominated region. Band-to-band photoluminescence imaging has been used to study the minority charge carrier lifetimes in these wafers after different processing steps. Despite the different defects found in the different regions of the wafers carrier lifetimes appear to be uniform across the entire wafers, both for ungettered and gettered samples. Only after an oxidation process at 1100 °C oxygen related ring patterns become visible. It is, however, difficult to identify the band structure of the transition area between the regions among all the striations in the crystal.

The microstructure of highly dislocated stacking fault regions (dislocation density >106 cm−2) in industrial cast multicrystalline silicon has been investigated by light microscopy, scanning electron microscopy, and transmission electron microscopy. Our observations indicate that stacking faults form strong barriers to lattice dislocation movement and to the formation of sub grain boundaries. Stepped and curved stacking fault edges appear to generate dislocations. The observations suggest that stacking faults play an important role in the plasticity as well as in the formation of the microstructure of dislocations in multicrystalline silicon.

Dislocation etch-pit structures on multicrystalline silicon rods deformed at 900°C in four-point bending were studied prior to and after a high-temperature annealing. After deformation, the majority of the dislocation etch-pits were aligned along traces of {111} planes. Certain localized areas revealed network structures, where etch-pit arrays deviated in the range of 2-10° from the {111} plane traces. After annealing at 1350°C for 12h, a marked change in dislocation density and structure which varied from grain to grain was observed. Some grains showed incomplete polygonized structures, with notable irregularities and Y-junctions. The results were compared with observations on as-cast industrial multicrystalline silicon wafers for solar cells, where similar incomplete polygonized structures can be found.

A crystal is known to achieve lower energy if lattice dislocations are re-arranged in arrays forming a sub-grain boundary through a recovery process. Interaction of boundary dislocations with glide dislocations is also expected to bring about local equilibrium. In this work, dislocations localised in the vicinity of a sub-grain boundary (mis-orientation ) are studied in detail by transmission electron microscopy in order to determine their source. Contrary to the processes described above, it appears that the sub-grain boundary is the source of these dislocations, which are emitted from some locally stressed parts of the boundary. Several slip systems have been activated along the boundary resulting in high density of dislocations. It appears, further, that dislocation propagation from one or more sources is disrupted by interaction with other dislocations or other defects. The dislocations from various sources will be piled up against the obstacles of the other, resulting in the localization of the dislocations close to the sub-grain boundary

Highly detrimental dislocation clusters are frequently observed in lab-scale as well as industrially produced multicrystalline silicon ingots for solar cell applications. This paper presents an investigation of dislocation clusters and how they develop over the whole height of a pilot-scale ingot. A 12-kg ingot, cast in a pilot-scale directional solidification furnace using a standard slip cast silica crucible and standard coating containing silicon nitride powder, was studied with respect to dislocation clusters. Dislocation clusters originating from grain boundaries were identified and followed from an early stage to the top of the ingot. One possible model for growth and multiplication of the dislocations in the clusters during solidification where slip on the {11¯0}〈110〉 system must be allowed is described in detail. Another possible mechanism is also discussed.

This study is focussed on the growth of multicrystalline silicon ingots with large grains by controlling the silicon melt cooling rate to initiate dendritic nucleation in the initial stage of the solidification. Two ingots were grown with different undercooling rates and compared with a reference ingot grown by standard cooling conditions. All ingots were grown in a lab scale directional solidification system. The wafers cut from all three ingots have been characterized for resistivity, minority carrier lifetime and dislocation density measurements by four point probe, quasi steady state photo conductance and PV Scan, respectively. The wafers were converted into solar cells and their electrical parameters have been measured. The cells fabricated from ingot 2 show slightly higher efficiencies in comparison with ingot 1 and the reference one. The present cooling rate was not enough to initiate the dendrite nucleation in the beginning of the solidification. Hence, there is no significant difference was observed in the crystal quality of the grown ingots 1 and 2.

The microstructure of commonly occurring dislocation patterns in industrial directionally solidified multicrystalline silicon has been systematically studied by light microscopy, electron backscatter diffraction, and transmission electron microscopy. The work has been focused on dislocation clusters on wafers near the top of cast blocks. In near {111} grain surface, dislocation arrays parallel to {110} plane traces are lying in parallel rows of {111} planes inclined to the surface, in mainly 〈112〉30∘ orientation. The dislocation configuration suggests that the microstructure may result from a recovery process. The dislocations formed during crystal growth and cooling have undergone transformations at high temperature in order to achieve low energy configurations for minimization of dislocation and crystal energy.

The focus of this work is the development and characterisation of 156x156 mm2 sized industrial type screen printed silicon solar cells made of 100% solar grade silicon (SoG-Si). The feedstock under investigation is produced by 6N Silicon Inc. from metallurgical grade silicon with a lower cost low energy refining technique compared to the Siemens process. Solar cells were processed at ISC Konstanz with industrial type process equipment. Defining a stable baseline process at ISC Konstanz, the improvements of the 6N Silicon material achieved during one year were tested against a single polysilicon reference brick. In addition, process enhancements leading to higher efficiencies were investigated. Reaching the same average efficiency level for reference and 6N material applying the baseline process, an advanced process which still satisfies industrial production standards was defined. Running this advanced process achieved an average efficiency of 16.0% with 100% 6N Silicon feedstock, and a best cell having 16.3% efficiency. The four best cells of both materials and both processes are further characterised via SR, LBIC and thermography measurements to show material dependent characteristics on cell level. Reverse current behaviour and LID are tested for cells of different ingot positions which are relevant information for module manufacturers.

The focus of this work is the development of large area industrial type screen printed silicon solar cells made of 100% solar grade silicon (SoG-Si). The feedstock under investigation is produced by 6N Silicon Inc. from metallurgical grade silicon with a lower cost low energy refining technique compared to the Siemens process. Solar cells were processed at ISC Konstanz with industrial type process equipment. This work was conducted over a one year period, where the material quality was improved and individual process steps were enhanced or adapted to the properties of the SoG-Si. These efforts made on both sides of the production chain resulted in solar cells that exceed 16% efficiency on standard 156×156 mm2 sized substrates made of 100% 6N Silicon material. For the purpose of this study, the 6N Silicon feedstock was processed into multicrystalline silicon ingots. These ingots achieved bulk resistivities between 0.5-2.5 Ωcm. The 6N purification approach uniquely applies an Al-Si melt as the primary purification step. The aluminium content of the feedstock end product, however, was observed to be lower than 0.05 ppmw. The overall contamination levels are sufficiently low to meet the needs of a solar cell producer. With a stable baseline process at ISC Konstanz, the improvements of 6N Silicon material were tested against a single polysilicon reference brick. In addition, process enhancements leading to higher efficiencies were also investigated. The same average efficiency level as the polysilicon reference was reached with the 6N material by applying the baseline process. An advanced process was then defined that still satisfies industrial production standards. This advanced process includes a novel isotexture, an adapted shallow POCl3 diffusion, new metallisation paste and a new front side grid design. Running this advanced process achieved average efficiency of 16.04% with 100% 6N Silicon feedstock, and a best cell having 16.3- - 3% efficiency.

On the growth of dislocationclusters in directionally solidified multicrystalline silicon ingots by slip on the{11 0} slip systems