Integrated circuits based on thin-film transistors (TFTs) are attractive for use in many areas, including the Internet-of-Things (loT), where ultra-thin circuits on flexible substrates at a low-cost per unit area provide significant advantages over silicon CMOS. A complete loT circuit based on TFTs requires complex digital circuits to perform embedded control and signal-processing calculations. In this work, we have demonstrated a microprocessor capable of such complex computations and showcase it by running a complex assembly code. We selected the MOS 6502 for this, as it was one of the most commonly used microprocessors in the late 1970s, when applications with embedded software started to emerge. The 6502 came in various, more advanced iterations through the following decades [1]. The Flex6502 has been fabricated in an 800nm Indium-Gallium-Zinc-Oxide (IGZO) TFT process technology, manufactured on a flexible polyimide substrate, with total thickness less than 30µm. Based on the comparison of two logic styles, pseudo-CMOS logic [2] and resistive load logic [3], we selected pseudo-CMOS as the better-suited logic family for robustness and energy efficiency. We used the assembly code of the well-known Snake game to demonstrate real-time correct operation of the circuit.

Flexible Integrated Circuits (FlexICs) allow for ultra-thin intelligence to be added to wearable systems, reducing or eliminating the need for bulky rigid components and dramatically improving both form factor and cost of the final device. A flexible Successive Approximation Register Analog to Digital Converter (SAR-ADC) utilizing a resistive Digital to Analog Converter (DAC) has been demonstrated, allowing for an electrical interface to external transducers. Alongside approaches to simplify on-device calculation and wireless communication which have been validated in FlexICs, the design and included building blocks may be customized to enable a wide range of on-body sensing applications oriented towards comfortable, unintrusive monitoring approaches.

The recent developments in the field of large area, flexible and printed electronics have fueled substantial advancements in Laser Printing and Laser Sintering, which have been attracting interest over the past decade. Resulting applications, ranging from flexible displays and sensors, to biometric devices and healthcare, have already showcased transformational advantages in terms of form factor, weight and durability. In HiperLAM project, Laser-Induced Forward Transfer (LIFT), combined with high speed laser micro-sintering are employed, as digital microfabrication tools for the demonstration of fully functional RFID antennas and fingerprint sensors based on highly viscous Ag and Cu nanoparticle inks. Having previously successfully demonstrated complex structures, this work's focus is on increasing the process throughput and yield by increasing the laser repetition rate (up to 40 kHz) and scanning speed (up to 2 m/s), without compromising reliability and resolution. In order to gain insight into the effects of the incremented repetition rate on the printing procedure, the latter was monitored in real time via a high-speed camera, able to acquire up to 540.000 fps, coupled to the setup. Examples of resulting structures comprise well-defined interdigitated and spiral micro-electrodes with post-sintering electrical resistivity lower than 5 x bulk Ag and 3 x bulk Cu. The aforementioned results validate the compatibility of laser based processing with the field of flexible RFID tags and OTFT based fingerprint sensors and foster the wider adoption of LIFT and laser micro-sintering technology for laboratory and industrial use.

Recent advances in flexible electronics have highlighted the importance of high throughput, digital additive microfabrication techniques. In this work, we demonstrate the combination of laser printing and laser sintering of a novel copper nanoparticle ink onto flexible substrates in order to produce oxide free conductive copper patterns in ambient atmospheric conditions. The printed patterns exhibit high reproducibility, very low resistivity (about 2x bulk), and negligible oxidation according to Raman spectroscopy. The process has been employed for the fabrication of an on-chip antenna on a flexible substrate for use in combination with a flexible circuit, in applications where a small form factor and simplicity of integration are required alongside ultra-low cost, e.g. consumable tagging. (C) 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

The integration of flexible integrated circuits (FlexICs) on flexible plastic substrates to deliver smart flexible electronic solutions has enormous potential across a range of consumer markets, including wearable devices, healthcare devices and smart labels. At present, reliable FlexIC integration for hybrid flexible electronic circuits is mainly based on conductive adhesive packaging which is too slow and/or expensive to address the highest volume products envisioned for consumer markets. In this research we have investigated low-cost bonding processes for FlexICs based on non-conductive adhesive (NCA) and thermosonic-adhesive (TS-A) bonding. Four-wire resistance tests, shear tests and bending tests were used for evaluation during process development. The results confirmed that NCA and TS-A bonding were feasible for FlexIC packaging, and the evaluation tests showed encouraging electrical and mechanical performance. This research is bringing novel bonding techniques that will significantly advance the development of low-cost manufacturing of smart flexible electronics to drive mass market adoption in consumer markets.

In this manuscript, the authors investigate the growth of indium zinc oxide, indium zinc oxide (InZnO, IZO) as a channel material for thin-film transistors. IZO is grown at atmospheric pressure and a high deposition rate using spatial atomic layer deposition (S-ALD). By varying the ratio of diethylzinc and trimethylindium vapor, the In/(In + Zn) ratio of the film can be accurately tuned in the entire range from zinc oxide to indium oxide. Thin film transistors with an In to Zn ratio of 2:1 show high field-effect mobility—exceeding 30 cm2/V s—and excellent stability. The authors demonstrate large scale integration in the form of 19-stage ring oscillators operating at 110 kHz. These electrical characteristics, in combination with the intrinsic advantages of atomic layer deposition, demonstrate the great potential of S-ALD for future display production.

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self‐aligned (SA) top gate amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) TFT characteristics. Finally an optimized layer was integrated in TFT backplane on polyimide (PI) foil and a QQVGA AMOLED display is demonstrated.

Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these.

In this work, the design of a low-voltage line driver in a complementary organic technology on foil is presented. The behavior and the variability of circuits are predicted by means of transistor modeling and statistical characterization. The comparison of measurements and simulations of simple digital blocks verifies the effectiveness of the design approach. A transmission-gate based 32-stage line driver and a fully-static one are shown. It is also shown that, based on the statistical OTFT characterization, the fully-static logic style is a more suitable choice for implementing line drivers in this technology. The implemented fully-static line driver, which is comprised of 1216 transistors, has the highest transistor count reported for a complementary organic circuit to date. It works at supply voltages from 10 V to as low as 3.3 V, reaching a 1 kHz clock frequency, and occupying an area of 25x4.7 mm2. The drivers are implemented in a technology compatible with that of flat-panel display backplanes and are tested with a QQVGA AMOLED display.

We demonstrated self-aligned amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistors (TFTs) where the source–drain (S/D) regions were made conductive via chemical reduction of the a-IGZO via metallic calcium (Ca). Due to the higher chemical reactivity of Ca, the process can be operated at lower temperatures. The Ca process has the additional benefit of the reaction byproduct calcium oxide being removable through a water rinse step, thus simplifying the device integration. The Ca-reduced a-IGZO showed a sheet resistance (RSHEET) value of 0.7 kΩ/sq., with molybdenum as the S/D metal. The corresponding a-IGZO TFTs exhibited good electrical properties, such as a field-effect mobility (μFE) of 12.0 cm2/(V s), a subthreshold slope (SS−1) of 0.4 V/decade, and an on/off current ratio (ION/OFF) above 108.

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

In this study, we have compared the performance of self-aligned a-IGZO thin-film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiNx interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field-effect mobility (mu(FE)) of over 10.0 cm(2)/(V.s), sub-threshold slope (SS-1) of 0.5 V/decade, and current ratio (I-ON/I-OFF) over 10(8). However, under negative-bias-illumination-stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma-treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel.

Our goal is to create thin low-cost flexible NFC tags to allow everyday objects to communicate to smartphones and computers and thus participate in the Internet of Things. We employ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor circuits processed at low temperatures, less than 250C, directly on thin polyester substrates. Reaching NFC standards with a-IGZO circuits is challenging because the technology is n-type only and the electron mobility (~15cm7Vs) is lower compared to silicon. As the main result, we show that the most important NFC regulatory standards are met, even with relaxed 5 micron design rules, using optimized design topologies.

We describe the device and transport characteristics of amorphous zinc tin oxide thin‐film (ZTO) transistors. In samples with a sufficiently high mobility and at a high gate voltage, a crossover occurs from transport governed by thermal excitation of trapped charges to one where the charge carriers reside for a sufficiently long time in extended states. Very few semiconductors exhibit this range of behavior in the same device under different conditions. We also describe the correct methods to extract mobility values and ionization energies from current voltage characteristics.