In the framework of energy transition, the massive insertion of Variable Renewable Energies leads to think to new ways of controlling and stabilizing electrical networks. Small Modular Reactors (SMRs) could be a sustainable solution if they are proven to be flexible enough. Previous studies have shown the positive influence of SMRs on grids at short-time scales due to inertia and frequency regulation phenomena. In addition, this article aims at studying the influence of constrained grid events on nuclear systems safety and operation. The models of a power system dynamics (PowerFactory) and a nuclear dynamics software (CATHARE) are compared and chained. Two application cases are carried out to quantify the impact and the relevance of this chaining: a short-circuit and a load loss. This article finally concludes that this chaining is relevant to accurately simulate nuclear reactor behavior following grid events. Moreover, a chaining could be insufficient for electrical simulations after severe events such as short-circuits or for high nuclear insertion's rate in an energy mix, a coupling, i.e co-simulation, could be considered.

Photovoltaic (PV) powered Electric Vehicle Charging Stations (PVCS) have received extensive attention recently due to the complementary relationship of PV energy and electric vehicles. This paper proposes a methodology aimed at assisting a Charging Point Operator (CPO) in determining the size of the main components of such PVCS. The modular structure of the method gives flexibility for possible use on a new sizing problem by modifying key parameters such as the EV charging demand (i.e., arrival/departure times and energy needed to fill the battery), the EV charging strategy or the business model, independently from each other. It is of particular interest for a CPO that sizes many PVCS operated in the same environment (for example, a car park at a workplace). In that case, the CPO first has to apply the method on a representative charging station. Next, he can re-use parts of the obtained results to drastically speed up (from weeks to hours) the sizing of the other charging stations. The proposed method has been applied to the EVCS of an industrial research complex in southern France. The input dataset used to apply the method consists of more than 32,000 charging transactions spanning over 6 years with 350 EV users and 80 charging points. Three charging strategies with different levels of complexity are investigated, including Mean Power, Plug and Charge, and Solar Smart Charging. The considered business model is based on the maximization of the self-production rate. The numerical findings reveal that employing a straightforward charging strategy, such as Mean Power, leads to a substantial reduction of nearly half in the required size of the PV plant compared to the basic Plug and Charge mode. In addition, our analysis demonstrates that Solar Smart Charging has the potential to decrease the PV plant size by nearly three times.

In the current renewable energies’ expansion framework, the increasing part of intermittent electricity production sources (solar or wind farms) in the energy mix and the reducing part of thermal power stations that are nowadays useful to ensure grid stability will lead to a complete paradigm shift concerning the means to ensure grid stability. Nuclear energy, which is carbon-free and dispatchable, may be a sustainable solution to this grid reliability issue if it is adequately designed and implemented on the grid. Several solutions aiming at improving the future nuclear power flexibility are currently under investigation in the literature, among them are those based on Small Modular Reactor (SMR) plants. In order to demonstrate their potential ability to stabilize electric grids, it is necessary to perform electrical dynamic simulations taking into account a spatial and temporal discretization of the grid. In this paper, such calculations are performed using the PowerFactory software. This tool can reproduce electrical grids thanks to models of turbo generators, lines, transformers, loads, I&C systems, etc. The objective is to assess to what extent the innovative SMR features may enhance the frequency control of a grid. For this purpose, a short-circuit event and three frequency stability criteria are firstly defined. Then, a verification of the correct behaviour of the IEEE 39-bus (or New England) grid with regulations is carried out. The relevance of implementing Small Modular Reactors (SMR) instead of large power plants on such frequency stability criteria on this grid is finally assessed, in order to conclude in a preliminary way the possible contribution of small reactors to the future grid’s sustainability.

Sales of electric vehicles, for commercial use and personal use, keep rising. In parallel of the development of the associated Electric Vehicle Charging Infrastructure (EVCI), systems for controlling the charging of EVs will have to be developed in order to reduce the impact of such a development on the power grid. In this paper, we present a supervision system that controls the electric vehicle charging of employees of CEA Cadarache research center. The EVCI of Cadarache, set up in 2016, is constituted of more than 80 22-kW AC charging points spread over 30 zones. This EVCI currently supplies more than 376 vehicles including taxis, service vehicles as well as employees’ vehicles. This infrastructure is one of the largest private EVCIs in the region. The supervision system controls electric vehicle (EV) charging in real-time according to two objectives: respecting user preferences, by fully charging the EV battery, and synchronizing the power consumption of a fraction of the EVCI, i.e., 24 charging points, with the power production of a solar photovoltaic plant. This paper details the supervision system that is used to carry out these experiments and presents experimental results. These results show that it is technically feasible to increase (up to 60 percentage points) the self-production ratio while satisfying EV users.

While the number of embedded systems is continuously increasing, securing software against physical attacks is costly and error-prone. Several works proposed solutions that automatically insert protections against these attacks in order to reduce this cost and this risk of error. In this chapter, we present a survey of existing approaches and classify them by the level at which they apply the countermeasure. We consider three different levels: the source code level, the compilation level, and the assembly/binary level. We explain the advantages and disadvantages of each level considering different criteria. Finally, we encourage future works to take compilation into account when designing tools, to consider the problem of combining countermeasures, as well as the interactions between countermeasures and compiler optimisations. Going one step further, we encourage future works to imagine how compilation could be modified or redesigned to optimise both performance and security.

The security issues of devices, used in the Internet of Things (IoT) for example, can be considered in two contexts. On the one hand, these algorithms can be proven secure mathematically. On the other hand, physical attacks can weaken the implementation. In this work, we want to compare these attacks between them. A tool to evaluate and compare different physical attacks, by separating the theoretical attack path and the experimental parts of the attacks, is presented.

Physical attacks on cryptographic circuits were first identified in the late 1990s. These types of attacks, which are still considered very powerful, are generally classified into two main categories: "fault attacks" and "side-channel attacks." To secure circuits against such attacks, it is crucial to develop appropriate methods and tools that enable accurate estimates of the protection mechanism's effectiveness. Numerous studies have described such methods and tools but, to the best of our knowledge, these previous investigations have considered side-channel attacks or fault attacks but not the combination of the two types. The present article proposes a combined investigation of both main types of attack by describing them with the same terminology and the same algorithm. This approach is made possible by introducing the concept of "physical functions" as an extension of the concept of "leakage functions," which are widely used in the side-channel community. The paper represents a first step toward applying the strong theoretical background developed for side-channel attacks to the investigation of fault attacks. Besides, the proposed approach could potentially make it easier to combine side-channel attacks with fault attacks, which could certainly facilitate the discovery of new attack paths.

Hardware Trojans have emerged as a security threat to many critical systems. In particular, malicious hardware components can be inserted at the foundry for implementing hidden backdoors to leak secret information. In this paper, we present a new method to partition the circuit under test into blocks in order to obtain different side-channel signatures per chip. Each signature indicates which block is off or on in terms of the dynamic power switching activity. As a result, there are different co-existing decisions to more precisely detect the Trojan instead of one decision resulting from one side-channel signature. Moreover, this method detects in which block the Trojan exists. AES was used as an example to be divided into blocks. Sakura-G was used as an implementation target. The obtained results give four decisions to enhance Trojan existence and position. This paper also presents a methodology for Trojan detection using a cryptographic protocol to secure the detection process.

COGITO ( Runtime Code Generation to Secure Devices appel ANR INS 2013) est un projet de recherche académique centré sur la sécurité des composants embarqués. Le consortium du projet est constitué de deux laboratoires du CEA, de l'École des Mines de Saint-Étienne et de l'INRIA de Rennes (auparavant laboratoire XLIM de l'université de Limoges). Le projet a démarré en octobre 2013 et se terminera n mars 2017.

In the landscape of cybersecurity, a large field of research is dedicated to physical attacks since the publication of the first attacks in the early 1990s. Side-channel attacks can reveal the secret values processed in a circuit by observing physical quantities (power consumption, electromagnetic emissions, execution time, etc.). Physical attacks constitute an important threat against embedded systems; in particular, they are the most effective way to break implementations of cryptography. The Smart Cards industry is up with the design of countermeasures, and high security products embed a large set of hardware and software countermeasures. With the emergence of the Internet of Things, we observe a rapid increase of the number of communicating devices, which present various security needs, but also unequal levels of security [7]. Hence, we advocate for the design of tools to automate the application of Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. In the COGITO project, we focused on the use of runtime code generation to introduce behavioural variability in embedded systems. Indeed, behavioural variability is often used as a protection against physical attacks [6]. Security products embed hardware and software desynchronisation mechanisms to achieve variability in side-channels: for example clock jitters in hardware or dummy loops of random duration in software. We defined code polymor-phism as the capacity of a program component to vary its observable behaviour, at runtime, without altering its functional properties. Code polymorphism can be considered as a hiding countermeasure: the information leakage, which is observable physical quantities during the secured computation, is hidden in the information noise produced by the behavioural variability generated by the poly-morphism. However, code polymorphism alone does not remove information leakage as it would be the case with masking countermeasures. We implemented code polymorphism with runtime code generation of machine binary instructions (Fig. 1): the polymorphic component is composed of (1) dedicated runtime code generators, specialised for the targeted component so that it presents a low memory footprint and a short code generation time, and (2) of polymorphic instances which are the many code variants produced by the polymorphic code generator at runtime. In order to produce many code variants of the same functional component, the runtime code generator is driven by a source of random data. The successive execution of many polymorphic instances, which are all functionally equivalent but composed of different series of machine instructions, will induce a strong variability in the observable behaviour of the polymorphic component.

Among other threats, secure components are subjected to physical attacks whose aim is to recover the secret information they store. Most of the work carried out to protect these components generally consists in developing protections (or countermeasures) taken one by one. But this “countermeasure-centered” approach drastically decreases the performance of the chip in terms of power, speed and availability. In order to overcome this limitation, we propose a complementary approach: smart dynamic management of the whole set of countermeasures embedded in the component. Three main specifications for such management are required in a real-world application (for example, a conditional access system for pay-TV): it has to provide capabilities for the chip to distinguish between attacks and normal use cases (without the help of a human being and in a robust but versatile way); it also has to be based on mechanisms which dynamically find a trade-off between security and performance; all these mechanisms have to be formalized in a way that is clearly understandable by the designer. In this article, a prototype implementing such a security management system is described. The solution is based on a double-processor architecture: One processor embeds a representative set of countermeasures (and mechanisms to define their parameters) and executes the application code. The second processor, on the same chip, applies a given security strategy, but without requesting sensitive data from the first processor. The chosen strategy is based on fuzzy logic reasoning to enable the designer to describe, using a fairly simple formalism, both the attack paths and the normal use cases. A proof of concept has been proposed for the smart card part of a conditional access for pay-TV, but it could be easily fine-tuned for other applications.

We present a generic framework for runtime code polymorphism, applicable to a large class of computing platforms up to embedded systems with low computing resources (e.g. microcontrollers with few kilo-bytes of memory). Code polymorphism is de ned as the ability to change the observable behaviour of a software component without changing its functional properties. In our framework, code polymorphism is achieved thanks to runtime code generation, which oers many levers for code transformations: we describe the use of random register allocation, random instruction selection, instruction shuing and insertion of noise instructions.We evaluate the eectiveness of our framework against dierential power analysis and its overhead impact. As compared to a reference implementation of AES where the cipher key could be recovered by DPA in less than 50 traces in average, in our implementation the key cipher could not be extracted after 10000 traces. Our experimental evaluation shows a moderate impact in terms of performance overhead.

Physical attacks especially fault attacks represent one the major threats against embedded systems. In the state of the art, software countermeasures against fault attacks are either applied at the source code level where it will very likely be removed at compilation time, or at assembly level where several transformations need to be performed on the assembly code and lead to significant overheads both in terms of code size and execution time. This paper presents the use of compiler techniques to efficiently automate the application of software countermeasures against instruction-skip fault attacks. We propose a modified LLVM compiler that considers our security objectives throughout the compilation process. Experimental results illustrate the effectiveness of this approach on AES implementations running on an ARM-based microcontroller in terms of security overhead compared to existing solutions.

The paper reports the experimental validation of a new Bulk Built-In Current Sensor (BBICS) designed and implemented in a 40nm CMOS technology. The double-access architecture provides improved SEE detection as confirmed by laser experiments.

In this paper we study the information leakage that may exist, due to electrical coupling, between logically independent blocks of a secure circuit as a new attack path to retrieve secret information. First, an aes-128 has been implemented on a fpga board. Then, this aes implementation has been secured with a delay-based countermeasure against fault injection related to timing constraints violations. The countermeasure's detection threshold was supposed to be logically independent from the data handled by the cryptographic algorithm. Thus, it theoretically does not leak any information related to sensitive values. However experiments point out an existing correlation between the fault detection threshold of the countermeasure and the aes's calculations. As a result, we were able to retrieve the secret key of the aes using this correlation. Finally, different strategies were tested in order to minimize the number of triggered alarm to retrieve the secret key.

This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).

A Hardware Trojan is a malicious hardware modification of an integrated circuit. It could be inserted at different design steps but also during the process fabrication of the target. Due to the damages that can be caused, detection of these alterations has become a major concern. In this paper, we propose a new resilient method to detect Hardware Trojan based on path delay measurements. First, an accurate path delay model is defined. Then, path delay measurements are compared in a way that theoretically eliminate process and experimental variations effects. Finally, this proposed detection method is experimentally validated using different FPGA boards with substantial process variations. Both small sized sequential and combinatorial Hardware Trojans are implemented and successfully detected.