The GE/Lockheed Martin chip-on-flex (COF) multichip module (MCM) technology was developed to address high volume commercial applications where cost and size are critical design requirements. Single chip versions of the COF MCM process evolved as a workaround for those applications that had not solved the known-good-die (KGD) cost and availability issues. This paper describes the design, fabrication, assembly, and evaluation of a COF CSP (chip scale package) device with a number of design options. The evaluation includes thin and thick under-bump metallization, mask-defined and nonmask-defined I/O pads, and I/O pads located within, near and beyond the perimeter of the chip over the plastic encapsulation. The devices are assembled on a PWB with mini ball grid array (BGA) solder balls stencil printed on the CSP devices. Both underfilled and nonunderfilled assemblies are evaluated. The environmental testing focuses on thermal cycling to induce solder fatigue. The objective of this effort is to quantify life cycle predictions for various COF CSP configurations under different environmental conditions.

An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability