In this study, various fault tolerant techniques have been handled for pipelined MIPS-32 microprocessor in order for correct operation in the presence of faults and reliability analysis have been performed. For this purpose, register file is focussed on due to the fact that it is one of the most important unit of microprocessor. Register files designed with the fault tolerant methods have been synthesized with Cadence RTL Compiler, area and maximum frequency results have been obtained based on TSMC-90 nm technology. Mathematical models have been presented with the assumption that transient faults occur with a Poisson distribution and bit failures are statistically independent for reliability analysis. The results and graphics have been given by using Octave.

In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM. Keywords—serial peripheral interface(SPI), universal verification methodology(UVM), test, simulation.

This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM.

The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.

Embedded microprocessors are widely used in most of the safety critical digital system applications. A fault in a single bit in the microprocessors may cause soft errors. It has different affects on the program outcome whether the fault changes a situation in the application. In order to analyse the behaviour of the applications under the faulty conditions we have designed a custom verification system. The verification system has two parts as Field Programmable Gate Array (FPGA) and personnel computer (PC). We have modified Natalius open source microprocessor in order to inject stuck-at-faults into it. We have handled a fault injection method and leveraged it to increase randomness. On FPGA, we have implemented modified Natalius microprocessor, the fault injection method and the communication protocol. Then the “Most Significant Bit First Multiplication Algorithm” has been implemented on the microprocessor as an application. We have prepared an environment which sends inputs to and gets outputs from the Natalius microprocessor on PC part. Finally, we have analysed our application by injecting faults in specific location and random location in register file to make some classifications for effects of the injected faults.

To implement reliable digital systems, it is necessary to specify the capacity of testability. Particularly it is intensely important to test and detect faults in microprocessors in which be used in major system due to effect on whole system. In this paper, a microprocessor implemented in FPGA and a fault production circuit which is improved by being based fault injection method is entegrated and made a system. The processed faults with different type and model is given into the register file of the microprocessor and doing analysis. By developing a basic method an error detection circuit is designed, attached into the microprocessor and simulation and synthesize results of the system are showed.