The rise of chip multiprocessing or the integration of multiple general purpose processing cores on a single chip (multicores), has impacted all computing platforms including high performance, servers, desktops, mobile, and embedded processors. Programmers can no longer expect continued increases in software performance without developing parallel, memory hierarchy friendly software that can effectively exploit the chip level multiprocessing paradigm of multicores. The goal of this dissertation is to demonstrate a design process for data parallel problems that starts with a sequential algorithm and ends with a high performance implementation on a multicore platform. Our design process combines theoretical algorithm analysis with practical optimization techniques. Our target multicores are quad-core processors from Intel and the eight-SPE IBM Cell B.E. Target applications include Matrix Multiplications (MM), Finite Difference Time Domain (FDTD), LU Decomposition (LUD), and Power Flow Solver based on Gauss-Seidel (PFS-GS) algorithms. These applications are popular computation methods in science and engineering problems and are characterized by unit-stride (MM, LUD, and PFS-GS) or 2-point stencil (FDTD) memory access pattern. The main contributions of this dissertation include a cache- and space-efficient algorithm model, integrated data pre-fetching and caching strategies, and in-core optimization techniques. Our multicore efficient implementations of the above described applications outperform naïve parallel implementations by at least 2x and scales well with problem size and with the number of processing cores.

The focus of this work is to identify data partitioning strategies and their performance models for memory intensive two dimensional Magneto-Static Wave (MSW) calculations for shared memory architecture. We have constructed computing, communication and synchronization time models for the different data partitioning schemes. We have identified that improved performance for any scheme can be achieved by reduced boundary sharing, decreasing stride penalties, reduced synchronization requirement and increased data sharing. A maximum speed-up of 3.9 for the largest data size is observed for one — dimensional partitioning.

High performance computing is becoming critical in the medical area to aid real-time processing of complex analysis of biological signals. In this paper parallel schemes for real-time computations of pair-wise correlation (PWC) of electroencephalogram (EEG) signals, which belongs to streaming-data class of applications, are proposed and implemented and their performances are evaluated. Currently most of the EEG based diagnosis for epilepsy is done off-line. However, there is a growing need to perform these diagnoses in real-time to aid health care providers, including surgeons, in decision-making process that will lead to improved quality of life and prevent undesirable consequences, such as readmission to hospitals resulting in prolonged suffering and higher health care costs. Systematic study of the PWC problem and the IBM Cell Broadband Engine (CBE) architecture led us to a model that is well suited for the Cell architecture and GPUs. Measurements on the CBE indicate that speedup of 33.91 is possible over the serial code running on Intel Xeon processor and the schemes can be used for real-time signal processing.

The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex-II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62x for PV over an equivalent sequential software implementation. The average overall speed up of the CPU-FPGA implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The CPU-FPGA implementation also shows linear scaling with increase in the size of the input power network.

(1) Universita' del Sannio Research Centre on Software Technology RCOST Benevento, Italy (2) Universita' di Napoli "Federico II" Dipartimento di Scienze Fisiche and INFN Napoli, Italy Motivation In the past decade there has been an explosive growth of biological data, including genome projects, proteomics, protein structure determination, cellular regulatory mechanisms, and the rapid expansion in digitization of patient biological data. Although raw computational power follows "Moore's Law", the genomic data at GenBank (the NIH genetic sequence database, an annotated collection of all publicly available DNA sequences) is doubling every six months. Proteomic and cellular imaging data appear to grow even faster. Post-genomic-era bioinformatics will require high-performance computing power of the order of several hundreds of teraflops or more. Moreover a growing number of related problems is posed as complex optimization. Methods In recent years, FPGAs, short for Field-Programmable Gate Arrays, logic programmable chips [1] [2] have emerged as high-performance computing accelerators capable of implementing finegrained, massively parallelized versions of computationally intensive algorithms [3]. In particular several problems arising in biomedical and bioinformatics research can be viewed as finding the optimal covering of a finite set [4] [5]. While the Set Covering problem is known to be NPcomplete [6] a number of approximation heuristics have been proposed. The most efficient schema remains the greedy one [7]. Recently, a new greedy algorithm for approximating minimum set cover has been presented [8]. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. It shows very good empirical performances and it has successfully been applied in wireless network applications [9] [10]. While efficient implementations are given, the cost of probability distribution evaluation can still be unaffordable in massive realtime applications. In this paper we describe an implementation based on a FPGA of a tailored version of the algorithm. It makes the algorithm suitable for several real world bioinformatics problems. Results The test results show very good empirical performances on the used benchmarks. The speed up of our approach is also successfully tested.

The new generation of shared memory multi-core processors with multiple parallel execution paths provides a promising hardware platform for applications with high degree of task-level parallelism (TLP). Genetic Algorithm (GA), a widely-used evolutionary meta-heuristic optimization method, is a unique candidate in this class of applications and demonstrates significant amount of explicit and implicit parallelism. In this paper, we present the performance characteristics of a GA optimizing a placement problem on a Sun UltraSPARC T1 processor. To investigate the behavior of the benchmark, we vary both algorithm-specific parameters as well as the size of the target problem. The system performance is evaluated by monitoring throughput, cycle-per-instruction (CPI) and, the memory access patterns for different core and thread combinations. Our experiments show that for a constant data size, as the number of threads per core increase from 1 to 4, the throughput of the system increases by 84% keeping all cores active. Similarly, as we increase the number of cores in the system, the throughput of the system increases by a factor of 3. The average memory bandwidth is seen to scale in proportion to throughput for both core-scaling and thread-scaling. The overall increase in throughput, either by core-scaling or thread-scaling, in spite of growing memory bandwidth, shows the ability of the multi-threaded multi-core processor to hide long latency memory accesses for the targeted benchmark.