The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs with a specified irregular degree distribution. These code parameters were chosen simply because they satisfied a project design constraint, but the process described can be extended to most other low-density designs. Some new insights into the codepsilas performance curve behavior in the low error region under message passing decoding are presented.

The traditional method to estimate code performance in the higher SNR region is to use a sum of the contributions of the most dominant error events to the probability of error. If an ML decoder is used, these events will be minimum distance codewords; the traditional decoder used in LDPC codes, some variant of the message passing algorithm, will introduce non-codeword error events known as trapping sets. For long LDPC codes it is difficult to enumerate all of these dominant error events. A procedure to efficiently find dominant error events by using the regular low-density structure of an LDPC code is presented here. The search method can be adapted to work with LDPC codes of various regular and irregular degree distributions, but is especially suited to a very practical subset of LDPC known as regular {3, 6} codes of moderate block length. We also show how codes with very low error floors can be created by utilizing this search method.

This paper outlines a three-step procedure for determining the low bit error rate performance curve of a wide class of LDPC codes of moderate length. The traditional method to estimate code performance in the higher SNR region is to use a sum of the contributions of the most dominant error events to the probability of error. These dominant error events will be both code and decoder dependent, consisting of low-weight codewords as well as non-codeword events if ML decoding is not used. For even moderate length codes, it is not feasible to find all of these dominant error events with a brute force search. The proposed method provides a convenient way to evaluate very low bit error rate performance of an LDPC code without requiring knowledge of the complete error event weight spectrum or resorting to a Monte Carlo simulation. This new method can be applied to various types of decoding such as the full belief propagation version of the message passing algorithm or the commonly used min-sum approximation to belief propagation. The proposed method allows one to efficiently see error performance at bit error rates that were previously out of reach of Monte Carlo methods. This result will provide a solid foundation for the analysis and design of LDPC codes and decoders that are required to provide a guaranteed very low bit error rate performance at certain SNRs.

Although the standard Belief Propagation (BP) message pass ing algorithm (MPA) performs the exact maximum aposteriori (MAP) bit probability calculation for LDPC graphs with no cycles, there is no reason to believe that this algorithm is optimal for graphs w ith cycles. A number of modifications to the BP algorithm have been proposed, some of which simplify t he algorithm in exchange for a small performance degradation, while others add complexity and i ncrease decoder performance. These new decoders are typically only considered in the lower SNR regi on, or ‘waterfall’ portion of the performance curve. Since there are an increasing number of applica tions which require knowledge of code performance at very low error rates, it is instructive to com pare decoder performance in this SNR region. This paper explains how to use some newly developed low bit error rate analysis tools to efficiently evaluate the performance of a number of MPA modifications in t he high-SNR region.

Regular LDPC codes are a special class of lowdensity codes having an equal number of ones in each row and column of the parity check matrix describing the linear code. The uniform structure of regular LDPC codes allows a practical hardware implementation which can efficiently utilize the inherent parallelism of the message passing algorithm (MPA) commonly used to decode low-density codes. The class of {3, 6} LDPC codes has been extensively studied and they have been proven to provide very good error performance, especially at lower SNR. {4,8} codes have not been analyzed nearly as much in the literature, mainly because their 'threshold,' the SNR where the waterfall region of the error performance curve begins, is typically a quarter of a dB or so worse than for comparable-length {3, 6} codes. It has been proposed that {4,8} codes have better high SNR behavior, but until recently it was not possible to verify this conjecture. A new technique which can efficientlyfind errorfloors of LDPC codes now has the ability to illuminate just how good {4, 8} codes are in the high SNR region - a result which is of great interest for many practical applications. This paper will analyze the error floor characteristics of some {4, 8} codes and provide a simple algorithm for designing {4, 8} codes with low error floors. A newly-designed rate112 (1200,600) {4,8} code with a vastly superior error floor compared to codes of similar parameters is introduced.