A differential-drive Silicon Mach–Zehnder modulator is demonstrated, achieving a 3-dB bandwidth of 81.8 GHz. Despite limitations in the eye-diagram measurement setup, a PAM-8 eye-diagram was obtained at 100 Gbaud.

Co-packaged optics (CPO) has emerged as a promising solution to address the limitations of traditional pluggable optical transceivers, offering enhanced bandwidth, improved energy efficiency, and reduced signal loss. This paper presents a low-cost, volume-manufacturable Fan-Out Wafer Level Packaging (FOWLP) silicon photonic engine with an aggregate data transmission capacity of 1.79 Tbps (8 x 224 Gbps). The FOWLP platform enables the seamless integration of Electronic ICs (EICs) and Photonic ICs (PICs) without wire bonds, preserving signal integrity and minimizing losses. By demonstrating 112 Gbaud NRZ (112 Gbps/lambda) and PAM4 (224 Gbps/lambda) transmission with minimal digital signal processing, this work highlights the potential of silicon photonics for 200 Gbps/lambda Co-Packaged Optics (CPO) and Linear Pluggable Optics (LPO) applications. The findings underscore the enhanced signal integrity, power efficiency, and reduced latency achieved with FOWLP, addressing critical bottlenecks in hyperscale data centers and AI/ML clusters.

We successfully demonstrated 90 GHz Silicon Mach-Zehnder modulator using an integrated equalizer, which was fabricated using foundry standard silicon photonics technology. This potentially enables high volume manufacturable 1.6Tbps (200G/λ) and beyond IMDD transceivers.

A 1.6 Tbps (8-channel 224 Gbps/λ) Silicon Photonic Engine, fabricated using advanced electronic-photonic FOWLP, is successfully demonstrated for the first time, enabling low-cost, volume-manufacturable and highly scalable terabit photonic engines for CPO and LPO.

Silicon photonic integrated circuit (PIC) builds on the demand for a low cost approach from established silicon-based manufacturing infrastructure traditionally built for electronics. Besides its natural abundance, silicon has desirable properties such as optically low loss (at certain critical wavelengths), and small form factor to enable high density scaled-up optical on-chip circuitry. However, given its indirect bandgap, the platform is typically integrated with other direct bandgap (e.g., III-V semiconductor) platforms for on-chip light source. An effective solution to integrating light source onto silicon photonics platform is integral to a practical scaled-up and full-fledged integrated photonics implementation. Here, we discuss the integration solutions, and present our foundry's perspective toward realizing it.

Silicon photonics, as one of the most important emerging and enabling technologies, has been developed rapidly over the past two decades in the application areas such as optical communication, data center, and optical Lidar. In this chapter, instead of reviewing the standard CMO-based silicon photonics technology, we focus on the last mile technology toward production, namely the silicon photonics packaging technology. We will discuss the development efforts for fiber assembly, hybrid integration of light sources, etc. We also review the electronic and photonic co-packing, which is the most promising technology toward production. Finally, we will provide our insight into opportunities and challenges regarding the silicon photonics productization.

Thermo-optic phase-shifter is an important component widely used in various photonic applications such as optical neural network and LiDAR. Different methods have been proposed to improve the performance of the device. However, there is a lack of detailed quantitative comparison of such methods due to differences in fabrication platform and material properties. In this article, detailed investigation and comparison of 14 different thermal phase shifter designs on the same fabrication platform is provided. This includes the dimensions, material and heat dissipation approaches of the thermo-optic phase shifter. The comparison indicates that both suspended heater and doped silicon design could significantly improve thermo-optic phase modulation efficiency. On the choice of waveguide material, the electrical power consumption of SiN waveguide is about eight times higher than that of Si waveguide. Furthermore, the characterisation of thermal crosstalk and breakdown current of the thermo-optic phase shifters is also detailed. Such comprehensive investigation of thermo-optic phase shifters can serve as a useful design guideline for PIC designers.

An effective solution to integrating light source onto silicon photonics platform would be highly useful. Here, we discuss the integration solutions (i.e., hetero-epitaxial, heterogeneous and hybrid integration) and present foundry’s perspective toward implementing of such.

Conventional thermo-optic devices—which can be broadly categorized to that with and without a thermal isolation trench—typically come with a tradeoff between thermal tuning efficiency and tuning speed. Here, we propose a method that allows us to directly define the tradeoff using a specially designed thermo-optic phase shifter with an interleaved isolation trench. With the design, the tuning efficiency and speed can be precisely tailored simply by controlling the duty ratio (suspended length over total heater length) of the suspended design. Phase shifters are one of the main components in photonic-integrated circuits, and having phase shifters with a flexible design approach may enable the wide adoption of photonic applications such as an optical neural network and LiDAR.

In this work, IBM, CMC, AMF, and McGill University work together to verify a simplified packaging scheme for Si-photonic devices based on incorporating IBM’s polymer photonic interface into AMF’s Si-photonic fabrication process flow. The proposed procedure is used in packaging an O-band Si-photonic traveling wave Mach-Zehnder modulator (TW-MZM) yielding a fiber-to-fiber insertion loss of 16.5 dB and 16 GHz 3-dB bandwidth. Employing the packaged module without RF or optical amplification, we demonstrate the transmission of 28 Gbaud PAM4 (net 53 Gbps) over 2 km of SSMF using a linear feed-forward equalizer below the $2.4\,\,\times \,\,10^{-4}$ KP4-FEC BER threshold with 750 mVpp, and under the $3.8\,\,\times \,\,10^{-3}$ HD-FEC threshold at 500 mVpp. Besides, we transmit 36 Gbaud (net 67 Gbps) under HD-FEC at 830 mVpp. Operating with an RF driver; we transmit 70 Gbaud PAM4 below HD-FEC, which corresponds to a net rate of 131 Gbps. The achieved transmission performance highlights the potential of the proposed packaging scheme.

Many breakthroughs in the laboratories often do not bridge the gap between research and commercialization. However, silicon photonics bucked the trend, with industry observers estimating the commercial market to close in on a billion dollars in 2020 [45]. Silicon photonics leverages the billions of dollars and decades of research poured into silicon semiconductor device processing to enable high yield, robust processing, and most of all, low cost. Silicon is also a good optical material, with transparency in the commercially important infrared wavelength bands, and is a suitable platform for large-scale photonic integrated circuits. Silicon photonics is therefore slated to address the world's ever-increasing needs for bandwidth. It is part of an emerging ecosystem which includes designers, foundries, and integrators. In this paper, we review most of the foundries that presently enable silicon photonics integrated circuits fabrication. Some of these are pilot lines of major research institutes, and others are fully commercial pure-play foundries. Since silicon photonics has been commercially active for some years, foundries have released process design kits (PDK) that contain a standard device library. These libraries represent optimized and well-tested photonic elements, whose performance reflects the stability and maturity of the integration platforms. We will document the early works in silicon photonics, as well as its commercial status. We will provide a comprehensive review of the development of silicon photonics and the foundry services which enable the productization, including various efforts to develop and release PDK devices. In this context, we will report the long-standing efforts and contributions that previously IME/A*STAR and now AMF has dedicated to accelerating this journey.

We show a self-aligned compliant polymer interface between standard fiber connectors and nanophotonic waveguides with a polarization independent 1.1dB loss and a broadband response. The required chip interface is available through a commercial photonic foundry.

Scalability of silicon photonics packaging is required to support the growing demand for bandwidth in data centers and other emerging datacom and telecom applications. Connecting fiber to chip is still considered one of the main challenges of silicon photonics today due to the need for high alignment accuracy, which in turn requires expensive assembly machines and in most cases active alignment protocols. Furthermore, current fiber assembly technologies are not suitable for multiple emerging applications with large port count such as co-packaged optics. We present here the Photonic-plug technology, a unique self-aligning optical arrangement, which enables large assembly tolerance suitable for passive alignment protocols and for scalable silicon photonics port count packaging. The Photonic-plug technology accomplishes die stacking geometry with efficient wideband surface coupling as well as with grating coupler based silicon photonic chips. The combination of the Photonic-plug's large assembly tolerances and surface coupling geometry enables efficient silicon photonics wafer level testing capabilities prior to dicing. The Photonic-plug technology takes advantage from wafer level fabrication processes for planar and accurate implementing of optical elements. A library service model, called Photonic-bump, is incorporated as part of the Photonic-plug technology through silicon photonic wafer manufacturing process for complete removal of the fibers' mechanical constraints from wafer manufacturing process. The Photonic-plug takes fiber-to-chip packaging away from specialized, low throughput and expensive tools to standard, automated and high volume flip-chip packaging machines. Standardizing optical packaging through Photonic-plug methodology will affect further silicon photonics application to thrive such as photonic FPGA, optical interposers and chip-to-chip optical connectivity.

We report on the design, fabrication and testing of three types of coupling structures for hybrid chalcogenide glass Ge23Sb7S70-Silicon (GeSbS-Si) photonic integrated circuit platforms. The first type is a fully etched GeSbS grating coupler defined directly in the GeSbS film. Coupling losses of 5.3 dB and waveguide-to-waveguide back-reflections of 3.4% were measured at a wavelength of 1553 nm. Hybrid GeSbS-to-Si butt couplers and adiabatic couplers transmitting light between GeSbS and Si single-mode waveguides were further developed. The hybrid butt couplers (HBCs) feature coupling losses of 2.7 dB and 9.2% back-reflection. The hybrid adiabatic couplers (HACs) exhibit coupling losses of 0.7 dB and negligible back-reflection. Both HBCs and HACs have passbands exceeding the 100 nm measurement range of the test setup. GeSbS grating couplers and GeSbS-to-Si waveguide couplers can be co-fabricated in the same process flow, providing, for example, a means to first couple high optical power levels required for nonlinear signal processing directly into GeSbS waveguides and to later transition into Si waveguides after attenuation of the pump. Moreover, GeSbS waveguides and HBC transitions have been fabricated on post-processed silicon photonics chips obtained from a commercially available foundry service, with a previously deposited 2 μm thick top waveguide cladding. This fabrication protocol demonstrates the compatibility of the developed integration scheme with standard silicon photonics technology with a complete back-end-of-line process.

Benefiting from the 193-nm lithography, we have used one of the MPW platforms to realize narrow tip of width 100 nm with great repeatability and uniformity. Based on the new patterning technique, we optimized the suspended spot size converter (SSC) accordingly and the design result showed coupling loss less than -1 dB given with proper matching oil. We fabricated the device together with other photonic circuits and maintained the tip width around 105 nm across the wafers. First, we tested various matching oils, which are commercial product used for optical package but with unknown refractive index at C band, with one of them the SSC realized the state-of-the-art coupling loss less than -1.3 dB/facet with cleaved singlemode fiber (SMF) for both TE and TM polarization state with a remarkable polarization-dependent loss less than 0.5 dB. Subsequently, we tried customized matching oils, which are not suitable for massive production but with known refractive index, to further confirm the effect of the refractive index of the matching oil. A similar trend with simulation result was verified. We also tested many chips randomly selected from different wafers to check the statistics and uniformity of the device, the measurement result showed variation within 0.4 dB across wafers, which is the best performance to the best of our knowledge realized in the available silicon photonics platforms worldwide. Finally, to test the feasibility of the design for package, we studied the alignment tolerance and conducted a simple packaging using ultraviolet (UV) curing to fix the fiber and the silicon chip. The 1-dB extra loss corresponded to 2-mu m misalignment in cross section, similar to the tolerance between two cleaved SMF and the variation after UV curing was just 0.5 dB attributed to the loose alignment tolerance.

We experimentally investigate an optical link relying on silicon photonics transmitter and receiver components as well as a single section semiconductor mode-locked laser as a light source and a semiconductor optical amplifier for signal amplification. A transmitter based on a silicon photonics resonant ring modulator, an external single section mode-locked laser and an external semiconductor optical amplifier operated together with a standard receiver reliably supports 14 Gbps on-off keying signaling with a signal quality factor better than 7 for 8 consecutive comb lines, as well as 25 Gbps signaling with a signal quality factor better than 7 for one isolated comb line, both without forward error correction. Resonant ring modulators and Germanium waveguide photodetectors are further hybridly integrated with chip scale driver and receiver electronics, and their co-operability tested. These experiments will serve as the basis for assessing the feasibility of a silicon photonics wavelength division multiplexed link relying on a single section mode-locked laser as a multi-carrier light source.

We propose and experimentally demonstrate a novel scheme for simultaneous optical sensing of electric memory cell states. Results show that the effective sensing speed can be enhanced by 976 times with 100 nm spectrum ranges.

Summary form only given. Silicon photonics circuits are playing more and more important role in optical communication and interconnect fields [1, 2]. Many silicon CMOS technique compatible photonics integrated devices are reported [3, 4]. Most of those silicon components are based on optical waveguide. But conventional integrated optical waveguide is without memory feature. One hand, which makes us in trying to change the refractive index of the optical waveguide, must continually support energy to maintain the state of the waveguide, such as optical switch and modulators. And other hands, memory functional PIC into computer memory system, will solve van Neumann bottleneck issue.In this presentation, we propose and experimentally demonstrate two solutions. First one is a non-volatile optical waveguide structure. The schematic diagram, SEM pictures of the waveguide section are illustrated in Fig. 1. For checking the memory functionality, we made a microring resonator by memory optical waveguide. By measuring the optical spectrum, the memory properties of mantain and retention are proved. And using different pulse voltage to drive electrons will cause multi-level state in the optical spectrum. Another solution is using memristor device to control the optical waveguide property. The schematic diagram and SEM and TEM pictures are showing in Fig. 2. The SONOS as the memristor, series connect with P-N junction optical waveguide. The memristor situation determines the series current, thus change the optical waveguide states. Similarly, we fabricate a microring resonator with P-N junction waveguide. SONOS controlled current to modify the microring resonator's oscillation wavelength. From optical spectrum, we will know the SONOS status. We believe those kind of memory functionality silicon PIC should useful for green photonic circuits. In memory input/output interface, will enhance the memory cell sensing speed ~1000 times.

Benefiting from the new 193nm lithography, a narrow tip with width of 100 nm can be fabricated on IME’s MPW platform. Based on the new capability, we optimized the suspended coupler and realized the state-of-the-art coupling loss less than -1.3 dB/facet with cleaved single mode fiber. A uniformity of 0.4 dB across wafers has also been confirmed, the best performance to our knowledge realized in public-available silicon photonics platform.

Micron-scale disk resonators are explored to minituarize and enhance Ge-on-Si photodetectors. A 2.0 μm-radius detector exhibits a dark current of 11 nA, a responsitivity of 0.5 A/W and a 3-dB bandwidth of 17 GHz at -1V bias.