In Transactional Memory (TM) for multicore systems, contention management refers to the mechanisms used to guarantee forward to avoid performance pathologies, and to promote throughput. The choice of contention management police impacts strongly on the performance of applications. In this paper, we study contention management policies for Hardware Transactional Memory (HTM). Although the results were obtained from a HTM framework, the conclusions and proposals are applicable to any type of TM: hardware, software or hybrid. We first characterize transactions’ behaviors on execution time.We find that significant time is wasted when few transactions forward progress due to the data conflicts among different transactions. To reduce this kind of waste time, we propose a novel contention management(CM) scheme that reduces waste time and guarantees forwarding. We evaluate our techniques using a detailed execution-driven simulator. The results show that our scheme can effectively minimize the amount of waste time and, consequently, decrease execution time than previous approaches for large transactions.

Transactional Memory (TM) is one kind of approach to maximize parallel performance for multicore systems. There are conflicts When two or more parallel transactions access the same location and at least one access is a write. Contention management(CM) refers to the mechanisms used to guarantee forward—to avoid performance pathology, and to promote throughput. In this paper, we introduce a new CM police. We remitted six of seven performance pathologies summered by Bobba. Our result shows high performance for large transactions, while get moderate improvement or little slowdown for small transactions. The performance of the systems used this policies combined with other policy are steady.

Hardware Transactional Memory (HTM) is a promising Transactional Memory (TM) implementation because of its strong atomicity and high performance. Unfortunately, most contention management approaches in HTMs are dedicated to specific transaction conflict scenarios and it is hard to choose a universal strategy for different workloads. In addition, HTM performance degrades sharply when there are severe transaction conflicts. In this paper, we present a Global Contention Management Scheme (GCMS) to resolve severe transaction conflicts in HTMs. Our scheme depends on a Deadlock and Livelock Detection Mechanism (DLDM) and a Global Contention Manager (GCM) to resolve severe transaction conflicts. This scheme is orthogonal to the rest of the contention management policies. We have incorporated GCMS into different HTMs and compared the performance of the enhanced systems with that of the original HTMs with the STAMP benchmark suite. The results demonstrate that the performance of the enhanced HTMs is improved.

The transactional memory in multicore processors has been a major research area over past several years. Many transactional memory systems have been proposed to be used to solve the synchronization problem of multicore processors. Hardware transactional memory is one of the critical methods to speedup communications in multicore environment. In this paper, we give a review of the current hardware transactional memory systems for multicore processors. We take a top-down approach to characterizing and classifying various hardware transactional design issues and present a taxonomy of hardware transactional memory systems which is consist of the five fundamental design issues: version management, conflict detection, contention management, virtualization and nesting. Finally, we discussed the active research challenge: the relationship between transactional memory and Input/Output operations and system calls.

The transactional memory in multicore processors has been a very hot research area over past several years. Many transactional memory systems have been proposed to solve the synchronization problem of multicore processors. Software transactional memory is one of the critical methods to ease parallel programming and improve the scalability in the environment with many cores. In this study, software transactional memory systems for Multicore processors are reviewed according to the following aspects: transaction granularity, version management, conflict detection and synchronization. Finally, we discuss an active research challenge: whether strong isolation should be supported for the tradeoff between performance and semantics correctness in software transactional memory systems.

The transactional memory in multicore processors has been a major area of research over past ten years. Many transactional memory architectures have been proposed to solve the synchronization problem of multicore processors. Hardware transactional memory is one of the critical methods to speedup communications between many cores. We give a review of the current hardware transactional memory systems for multicore processors. Hardware transactional memory systems are classified into the following two categories: whether to support unbounded transactional memory and whether to support transactions nesting. Finally, we discuss two active research challenges: the relationship between transactional memory and input/output operations and instruction set architecture supporting.