In underwater wireless optical communication (UWOC) systems, using single-photon avalanche diodes (SPAD) as a detector can improve the detection sensitivity and thus improve the transmission distance. However, the signal detection for SPAD-based systems is greatly challenged by the complex optical channel characteristics and SPAD nonlinear distortion. In order to mitigate the nonlinear distortion caused by SPAD detectors, signal-dependent noise (SDN), and the effect of underwater channel attenuation on the transmitted signal in UWOC systems, this paper proposes a signal detection scheme using deep neural networks with embedded SDN variance (DNN–SDN). This scheme performs joint equalization and demodulation of the received signal, avoiding information loss and error propagation between these two processes, thereby achieving more accurate signal recovery. In this work, we first characterize the statistical noise model for the SPAD array and establish a nonlinear relationship between the number of detected photons and the transmitted signal power. The SDN variance is integrated as an input feature during network training. Performance is quantified via a joint loss function with parameters optimized through a systematic ablation study. Finally, the performance of the proposed signal detection scheme is also compared with other schemes in different waters. Simulation results demonstrate that the scheme can effectively mitigate the effects of SPAD-induced nonlinear distortion and SDN on the signal, and the proposed method extends the transmission distance by 20%–40%.

As the mainstream technology solution for deep imaging LiDAR, dToF measurement has been widely applied in emerging fields such as environmental perception and obstacle recognition, 3D terrain reconstruction, real-time motion capture, and drone obstacle avoidance navigation due to its advantages of high resolution, long-range detection capability, and high sensitivity. In order to adapt to functional applications in different scenarios, the resolution of TDC needs to be adjustable and can work normally in different environments. In view of this, this article studies the pixel array and TDC circuit in the chip and locks a voltage-controlled ring oscillator (VCRO) with the same structure as the pixel to a fixed frequency through a PLL structure. Then copy the control voltage of the locked VCRO to the control terminal of the TDC in each pixel. In an ideal situation, this control voltage can make the oscillation frequency of VCRO within the pixel consistent with the locking frequency of VCRO within the PLL, and insensitive to changes in PVT. This study developed a module expandable 16 × 16-pixel array dToF sensor chip based on TDC architecture using CMOS technology. Finally, six configurable 16 × 16-pixel subarrays were integrated and constructed into a 32 × 48 large-scale dToF sensor chip through modular splicing. The top-level layout design was completed using SMIC 180 nm technology, with a layout area of 5285 µm × 3669 µm. Post-simulation verification showed that, under the testing conditions of a 400 MHz system clock and a 33.3 kHz frame rate, the dToF chip system performance indicators were: time measurement resolution of 156 ps, DNL < 1 LSB, INL < 0.85 LSB, and absolute ranging accuracy better than 2.5 cm.

A high-real-time,high-quality infrared image equalization algorithm has been developed to address the frequent brightness or darkness in captured images caused by the image's large dynamic range and high-speed motion of the targets and cameras during target tracking with infrared cameras.The proposed algorithm adjusts the contrast between the image subject and background by optimizing the exposure parameters of the infrared camera.First,the image is partitioned by analyzing brightness variations in adjacent areas.Then,non-continuous area retrieval is performed to identify the image subject,which is weighted to calculate the image brightness.To support camera miniaturization,the interpolation method is combined with the lookup table method to iteratively adjust the exposure parameters based on the image's average brightness.This algorithm ensures image subject clarity,speed of infrared camera exposure adjustment,and eliminates the need for additional storage units.Infrared camera testing demonstrates that the proposed algorithm achieves infrared image equalization at an average speed of 3.2 frames per second with an average exposure error of 5.15%,highlighting its practical application value.

As the resolution and conversion speed of time-to-digital conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy. This paper presents a high-linearity, low-power-consumption, and wide dynamic range TDC that was achieved based on the SMIC 180 nm BCD process. Compared with previous research methods, the proposed phase arbiter structure can eliminate sampling errors and improve the linearity of TDC. The preprocessing circuit can eliminate fixed errors caused by START and STOP signal transmission delays. Post-simulation results show that the TDC has high linearity, with ranges of DNL and INL being −0.98 LSB < DNL < 0.93 LSB and −0.88 LSB < INL < 0.95 LSB, respectively. The highest resolution is 156 ps, the maximum measurement time range is 1.2 μs, and the power consumption is 1.625 mW. The overall system architecture of TDC is very simple, and it can be applied to dToF LIDAR to measure photon flight time, capable of measuring a range of up to hundreds of meters, with an accuracy of 2.25 cm, high linearity, and without any post-processing or time calibration.

The full text of this preprint has been withdrawn, as it was submitted in error. Therefore, the authors do not wish this work to be cited as a reference. Questions should be directed to the corresponding author.

As a key parameter, the timing jitter representing the temporal response of SPAD directly determines the performance of time-resolved imaging based on SPADs. In this paper, an accurate analytic model for predicting the temporal response of SPAD is presented. In which the avalanche build-up, avalanche spread and carrier transport in neutral regions was taken into account. Moreover, the depth-dependent avalanche triggering was incorporated. The results show that our predicted temporal response is closer to the measured data, and its accuracy is superior to that of the previous work. This indicates that our developed model can provide a reliable way to estimate the timing performance during the SPAD design and optimization.

With the rapid development of deep learning, weather recognition has become a research hotspot in the field of computer vision, and the research on field programmable gate array (FPGA) acceleration based on deep learning algorithms has received more and more attention, based on which, we propose a method to implement deep neural networks for weather recognition in a small-scale FPGA. First, we train a deep separable convolutional neural network model for weather recognition to reduce the parameters and speed up the performance of hardware implementation. However, large-scale computation also brings the problem of excessive power consumption, which greatly limits the deployment of high-performance network models on mobile platforms. Therefore, we use a lightweight convolutional neural network approach to reduce the scale of computation, and the main idea of lightweight is to use fewer bits to store the weights. In addition, a hardware implementation of this model is proposed to speed up the operation and save on-chip resource consumption. Finally, the network model is deployed on a Xilinx ZYNQ xc7z020 FPGA to verify the accuracy of the recognition results, and the accelerated solution succeeds in achieving excellent performance with a speed of 108 FPS and 3.256 W of power consumption. The purpose of this design is to be able to accurately recognize the weather and deliver current environmental weather information to UAV (unmanned aerial vehicle) pilots and other staff who need to consider the weather, so that they can accurately grasp the current environmental weather conditions at any time. When the weather conditions change, the information can be obtained in a timely and effective manner to make the correct judgment, to ensure the flight of the UAV, and to avoid the equipment being affected by the weather leading to equipment damage and failure of the flight mission. With the help of this design, the UAV flight mission can be better completed.

To improve the performance of orthogonal frequency division multiplexing (OFDM) systems in underwater wireless optical communication, a soft decision feedback equalizer (SDFE), which considers the impacts of signal non-negativity, channel estimation error, and signal-dependent noise (SDN), is proposed to suppress inter-carrier interference, thus being more suitable for the actual communication environment. Different from the conventional SDFE, the introduction of SDN makes the relationship between the received signal and the noise become complicated, and renders the turbo equalization framework inapplicable for OFDM systems. To solve this problem, we incorporate a Fourier transform and an inverse Fourier transform into the noise term and derive a series of specific expressions, leading to a modified approach compatible with the turbo equalization framework. Furthermore, both the a posteriori moments of estimated symbols and the a priori moments of unestimated symbols are used in our proposed SDFE, and a general expression for turbo equalization has been derived. To further reduce the computational complexity while obtaining the frequency reversal diversity and mitigating the error propagation, a bidirectional threshold-SDFE (BiT-SDFE) with a controllable inverse matrix update and a serially connected bidirectional structure is developed. Simulation results demonstrate that the bit error rate of the proposed equalizer significantly outperforms existing counterparts, especially in the case of high noise intensity and severe channel estimation error.

A phase-locked loop (PLL) circuit with low power consumption and 50% duty cycle regulation has been implemented using the SMIC 180nm BCD process. The circuit fulfils the clocking requirements within the system on chip (SoC) and employs a four-stage differential loop oscillator to generate the clock phase with a minimal footprint, facilitating straightforward integration. The duty cycle corrector is a single-ended structure. The incorporation of a gain-enhanced charge pump enhances the performance of the loop, concomitantly reducing voltage ripple. This results in improved accuracy and an extended input duty cycle range and operating frequency range. The results of the post-simulation analysis demonstrate that the duty-cycle corrector achieves a 50% output duty cycle over a wide input duty cycle range of 10 MHz to 1 GHz. The PLL lock time is less than 7 μs, the phase noise performance reaches −100.57 dBc/Hz@1 MHz, and the overall power consumption is 1.628 mW, with a core chip area of 0.059mm2.

As the resolution and conversion speed of Time-to-Digital Conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy. This paper presents a high linearity, low power consumption, and wide dynamic range TDC that has been achieved based on the SMIC 180 nm V3E BCD process. Compared with previous research methods, the proposed phase arbiter structure can eliminate sampling errors and improve the linearity of TDC. The preprocessing circuit can eliminate fixed errors caused by Start and Stop signal transmission delays. Post-simulation results show that the TDC has high linearity, with ranges of DNL and INL being − 0.76LSB < DNL < 0.89LSB, and − 0.59LSB < INL < 0.73LSB, respectively. The highest resolution is 150 ps, dynamic range is 2.5 ms, and the power consumption is 1.73 mW. The overall system architecture of TDC is very simple, and it can be applied to dToF LIDAR to measure photon flight time, capable of measuring a range of up to a kilometer, with an accuracy of 2.25 centimeters, high linearity, and without any post-processing or time calibration.

为了提高红外探测器模数转换的速度与精度,设计了一种用于非制冷红外焦平面阵列探测器片上14位10 MSps逐次逼近型模数转换器的高速比较器.本比较器采用前置放大器、动态高速度锁存器和新型输出缓冲器的三联级结构,并通过输入、输出失调存储的方式对各级放大器进行失调电压消除,使比较器工作的速度与精度得到提高.结果表明:基于TSMC 0.18 μm1P6M工艺进行设计与仿真,在电源电压为5 V的情况下,该比较器的采样速率为200 MSps,失调电压为32.63 V,传输延时为259 ps,-3dB带宽为1.11 GHz.该比较器相较于其他的设计,具有更小的失调电压以及传输延时,满足逐次逼近型模数转换器对其比较器速度与精度的要求.

Electro-optic (EO) modulators are typically made of inorganic materials such as lithium niobate; the replacement of these modulators with organic EO materials is a promising alternative due to their lower half-wave voltage (Vπ), ease of handling, and relatively low cost. We propose the design and fabrication of a push-pull polymer electro-optic modulator with voltage-length parameters (VπL) of 1.28 V·cm. The device uses a Mach-Zehnder structure and is made of a second-order nonlinear optical host-guest polymer composed of a CLD-1 chromophore and PMMA polymer. The experimental results show that the loss is 1.7 dB, Vπ drops to 1.6 V, and the modulation depth is 0.637 dB at 1550 nm. The results of a preliminary study show that the device is capable of efficiently detecting electrocardiogram (ECG) signals with performance on par with that of commercial ECG devices.

Polymer materials have the advantages of a low Young's modulus and low-cost preparation process. In this paper, a polymer-based optical waveguide pressure sensor based on a Bragg structure is proposed. The change in the Bragg wavelength in the output spectrum of the waveguide Bragg grating (WBG) is used to linearly characterize the change in pressure acting on the device. The polymer-based WBG was developed through a polymer film preparation process, and the experimental results show that the output signal of the device has a sensitivity of 1.275 nm/kPa with a measurement range of 0-12 kPa and an accuracy of 1 kPa. The experimental results indicate that the device already perfectly responds to a pulse signal. It has significant potential application value in medical diagnostics and health testing, such as blood pressure monitoring, sleep quality monitoring, and tactile sensing.

Grating couplers utilize light diffraction to achieve vertical coupling between waveguides and optical fibers. We proposed using SU-8 or polymethyl methacrylate (PMMA) polymer materials as the waveguide core layer and polydimethylsiloxane (PDMS) as the cladding layer for the grating coupler and completed the fabrication of both uniform and convergent grating couplers. We studied the effect of waveguide layer thickness, etching depth, and grating period on the uniformity of grating coupling performance. The influence of the convergence angle on the coupling performance of the convergence grating is investigated, and the optimal parameters are finally determined. The experimental results show that the coupling efficiency of the SU-8 uniform grating coupler reaches 30.1% and the 3 dB bandwidth is 70 nm when the grating period length is 4μm. For the SU-8 convergent grating coupler, the coupling efficiency reaches 40.0%, and the bandwidth is 65 nm when the convergence angle is 20°. The coupling efficiency of the PMMA grating coupler is lower than that of the SU-8 grating coupler; the coupling efficiency reaches 29.0% when the grating period of the uniform grating coupler is 4μm and 35.1% when the convergence angle of the convergent grating coupler is 20°.

为了解决7 nm布图设计中直通寄存器在自动布局时不能均匀分布且高宽比相差较大、纵向绕线较多的问题,提出在布图阶段提前布局直通寄存器,并将宏单元放置在模块上下两端以避开直通寄存器密集位置的优化方法;并针对7nm工艺对宏单元位置的约束,通过工具命令语言(TCL)脚本修复宏单元在布图阶段引起的违例.结果表明:相较于摆放在四周的布图规划,优化后的布图规划中建立时间最差负违例(WNS)减少0.131 ns,负违例总和(TNS)下降约80％,纵向拥塞从9.23％降至0.98％,功耗下降约500 mW;优化布图后执行TCL脚本,宏单元引起的违例下降了 288条,相较人工修复节约了 90％以上的时间.

As an electro-optic signal modulation device, the Mach-Zehnder (MZ) electro-optic modulator has potential applications in electrocardiogram (ECG) weak signal modulation. We propose a hybrid silicon/polymer asymmetric MZ electro-optic modulator that has the advantages of low half-wave voltages and low loss. The proposed modulator functions in the 1550 nm band, and it is mainly composed of two 3 dB multimode interference couplers, a bent waveguide, a modulation waveguide and a phase shifter. The loss of the multimode interference coupler is −0.43 dB at a device size of 4 $\mu \text{m}\,\,\times19.3\,\,\mu \text{m}$ . The core device size is 160 $\mu \text{m}\,\,\times700\,\,\mu \text{m}$ . The initial working state of the modulator is in the linear region, which can directly realize the linear modulation of voltage. Under the simulation condition of $\gamma _{33} =18.3$ pm/V, the results show that the modulator has a low loss of −3.4 dB and a low half-wave voltage amplitude of 3.0 V.

A waveguide Bragg grating (WBG) can facilitate an adaptable method for glucose monitoring according to the optical properties of polymer materials. We propose the design and fabrication of a WBG for glucose monitoring. By exploiting glucose oxidase as the upper cladding, polydimethylsiloxane was used as the substrate, and polymethyl methacrylate was used as the core layer. We investigated the effects of the diffraction order, waveguide structure, and grating period on the reflected spectrum of the WBG. Finally, process reproducibility after long-term storage and the capability to eliminate background solution interference (to achieve more specific glucose detection) were evaluated. The experimental results showed that when the glucose concentration was in the range of [0, 3.6] mg/ml, as the glucose concentration increased, the wavelength decreased approximately linearly, with a sensitivity of approximately 242.9 pm/(mg/ml) in the range of 0–2.7 mg/ml, while maintaining good selectivity and stability. The WBG for glucose monitoring has the advantages of a large measurement range and high sensitivity. This approach facilitates the application potential of such polymer material-based WBG photonic sensors in wearable technology and realizes the measurement of human blood glucose.

非制冷红外焦平面阵列(IRFPA)读出电路由于工艺制造或受环境条件的影响在正常运行时会产生非均匀性.针对传统电路存在的非均匀性问题,设计了基于12μm像元的非均匀性校正电路,该新型非均匀校正电路采用共源共栅电流镜产生电流,并且通过调节比例电流支路输出不同比例的电流,加入放大器负反馈结构提高电流精度,对像元阵列产生的非均匀性进行补偿.在TSMC 0.18μm工艺条件下进行仿真测试,新型校正电路进行校正之后,校正电流为368 nA.积分电流为44.24 nA,积分电路(CTIA)输出电压为3.81 V,积分时间缩短为255.43 ns,在不同的温度条件下,非均匀性问题降为3％以下,输出电压更稳定,满足设计条件.