For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

A novel high voltage polycrystalline silicon thin film transistor, with an improved on state and transient performance, is presented in this report. The key features of the new structure are the combination of a p/sup +/ drain and a semi-insulating field plate which connects the gate to the drain. Minority carrier injection from the p/sup +/ drain increases the on state current by a factor of 5 and reduces the 'turn on' time by over 10%. The minority carrier injection effects decay over sub-microsecond time scales.

We have recently demonstrated a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure. The key feature of this structure is the incorporation of a Semi-Insulating (SI) field plate which covers the entire offset region and connects the gate to the drain.Experimental results confirm that this device has a better voltage blocking capability than conventional Metal Field Plate (MFP) and Offset Drain (OD) HVTFTs and an improved on-state performance when compared to the OD structure.The impact of the SI field plate on device operation is analysed by simulating the on-state performance of both Semi-Insulating and conventional HVTFT structures. It is concluded that the SI HVTFT structure shows excellent potential for large area, high voltage microelectronic applications.

The fabrication and enhanced performance of a polycrystalline silicon high voltage thin film transistor structure, which incorporates a semi-insulating field plate, are reported. For comparison, the performance of conventional offset drain and metal field plate structures, fabricated on the same wafer using the same low temperature (⩽610 °C) polycrystalline silicon process, is described. Electrical characterization of the high voltage thin film transistor structures demonstrates that the new three terminal device offers the highest blocking capability (>200 V) without sacrificing on state performance.

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10−7 Ω−1.cm−1 Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.