The traditionally wired interfaces of many electronic systems are in many applications being replaced by wireless interfaces. Testing of electronic systems (both integrated circuits and printed circuit boards) still requires physical electrical contact through probe needles and/or sockets. This paper addresses the state-of-the-art, options, and hurdles-still-to-take of contactless testing, which would resolve many test challenges due to shrinking size and pitch of pads and pins and inaccessibility of advanced assembly techniques as System-in-Package (SiP) and 3D stacked ICs.

A method for wireless, noncontact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. The probe consists of a CMOS device with micro antenna structures and transceiver circuits. Each antenna and transceiver circuit is capable of probing one input/output (I/O) site on the DUT. Each I/O site on the DUT is connected to a single antennae and transceiver circuit, which is designed into the DUT. The antennae and transceiver circuits can be incorporated into the DUT without any impact on performance or real estate. The main advantage of noncontact wafer probing is higher reliability (less retest, no pad scrub marks), added functionality (higher test frequencies at higher pin densities), and increased throughput (higher parallelism, reduced alignment tolerance, less maintenance, and less downtime). The wireless probes interface to standard automated test equipment (ATE) while all antenna structures and electronics needed on the DUT are fully CMOS compliant