An interconnect, for transmitting an electrical signal between a first electronic device and a second electronic device, comprises a first coupling element immediately juxtaposed to, and separated by a dielectric barrier from, a second coupling element on the first electronic device, the first coupling element being electrically connected to an integrated circuit of the first electronic device. The interconnect further comprises a third coupling element immediately juxtaposed to, and separated by a dielectric barrier from, a fourth coupling element on the second electronic device, the fourth coupling element being electrically connected to an integrated circuit of the second electronic device. The third coupling element is electrically connected to the second coupling element. A digital to ultra-wideband pulse signal converter is electrically connected to the first coupling element such that, in operation, the first coupling element is driven with an ultra-wideband pulse to electromagnetically couple the first and second coupling elements.

I/O data throughput remains a bottleneck in high-speed chip to chip data communication. This paper discusses the latest technical innovations in increasing the I/O bandwidth while reducing energy per transition. Both wireline techniques that include DSP processing and equalization, and wireless transmissions that include on-chip inductive and capacitive coupling are discussed and compared.

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully CMOS compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.

In this paper, a new 3.1 GHz to 11.7 GHz ultra-wide-band (UWB) low-noise amplifier (LNA) is designed in 0.18-mu m RF CMOS process. The proposed circuit includes a common-source cascode amplifier followed by an output buffer stage. Special attention is paid to design of inter-stage circuit employing the combined shunt and double-series inductive peaking bandwidth enhancement technique. The amplifier exhibits a forward gain (S21) of 11.0-11.5 dB, a noise figure (NF) of 3.6-4.4 dB, and input return loss (S11) of less than -9.3 dB over the frequency range of 3.1 GHz to 11.7 GHz while consuming only 6.2 mW from a power supply of 1.5 V.

A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.