My talk today is going to be about trusted introductions for secure messaging, work by me and Adrian from ETH Zurich at the Network Security Group.

Although today’s most prevalent end-to-end encrypted messaging platforms using the Signal Protocol perform opportunistic encryption and provide resistance to eavesdropping, they are still vulnerable to impersonation attacks. We propose Trusted Introductions, a mechanism to transfer existing identity verifications between users, to increase resistance to active attacks. The proposal builds on the out-of-band user identity verification capabilities provided by the Signal Protocol. We argue that replacing user-managed identity-keys in cryptographic systems with the concept of an introduction, will increase users’ understanding and improve usability of the verification mechanism. Current events underscore the need for anonymous introductions, which can be achieved based on the Signal Protocol’s properties of forward secrecy and repudiation.

Path aware networking (PAN) is a promising approach that enables endpoints to participate in end-to-end path selection. PAN unlocks numerous benefits, such as fast failover after link failures, application-based path selection and optimization, and native interdomain multi-path. The utility of PAN hinges on the availability of a large number of high-quality path options. In an inter-domain context, two core questions arise. Can we deploy such an architecture natively in today's Internet infrastructure without creating an overlay relying on BGP? Can we build a scalable multi-path routing system that provides a large number of high-quality paths? We first report on the real-world native deployment of the SCION next-generation architecture, providing a usable PAN infrastructure operating in parallel to today's Internet. We then analyze the scalability of the architecture in an Internet-scale topology. Finally, we introduce a new routing approach to further improve scalability.

Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and real-time capable hardware implementation of a high quality EA method. In particular, we focus on the recently proposed permeability filter (PF) that delivers promising quality and performance in the domains of HDR tone mapping, disparity and optical flow estimation. We present an efficient hardware accelerator that implements a tiled variant of the PF with low on-chip memory requirements and a significantly reduced external memory bandwidth (6.4x w.r.t. the non-tiled PF). The design has been taped out in 65 nm CMOS technology, is able to filter 720p grayscale video at 24.8 Hz and achieves a high compute density of 6.7 GFLOPS/mm2 (12x higher than embedded GPUs when scaled to the same technology node). The low area and bandwidth requirements make the accelerator highly suitable for integration into SoCs where silicon area budget is constrained and external memory is typically a heavily contended resource.