Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability. In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability. To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.

Today's CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper [1] that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.

In the advent of multiple patterning techniques in semiconductor industry, metrology has progressively become a burden. With multiple patterning techniques such as Litho-Etch-Litho-Etch and Sidewall Assisted Double Patterning, the number of processing step have increased significantly and therefore, so as the amount of metrology steps needed for both control and yield monitoring. The amount of metrology needed is increasing in each and every node as more layers needed multiple patterning steps, and more patterning steps per layer. In addition to this, there is that need for guided defect inspection, which is in itself requires substantially denser focus, overlay, and CD metrology as before. Metrology efficiency will therefore be crucial to the next semiconductor nodes.ASML's emulated wafer concept offers a highly efficient method for hybrid metrology for focus, CD, and overlay. In this concept metrology is combined with scanner's sensor data in order to predict the on-product performance. The principle underlying the method is to isolate and estimate individual root-causes which are then combined to compute the on-product performance. The goal is to use all the information available to avoid ever increasing amounts of metrology.

At 28nm technology and below, hot spot prediction and process window control on production wafers have become increasingly critical to prevent sensitive pattern geometries from becoming yield limiting defects as a result of process variation. We previously established a systematic approach to identify focus-sensitive hotspots, characterize their process window margins, use a focus variation map to predict patterning defect locations, and verify predictions by guided e-beam inspection [1]. The current paper establishes the impact of intra-die micro-topography and its correlation with best focus variations of hotspots in a production chip layout. For this purpose, we obtain high-resolution topography measurements from an offline tool, and determine pattern-dependent best focus shifts from litho simulations to compare against the measured best focus distribution. We exercise the entire prediction and guided verification flow for after-etch application on a production use case with full-stack topography wafers.

Continuous tightening of the overlay control budget in the semiconductor industry drives the need for improved overlay metrology capabilities. In this context, measurement accuracy needs to be addressed. The first part this study shows that Diffraction Based Overlay metrology accuracy can be improved with a dedicated methodology. This methodology involves the use of target design simulation software in order to maximize stack sensitivity and to minimize processes non uniformity impact on the measurement. In the second part this study focuses on Holistic Metrology Qualification (HMQ) methodology that allows selecting the best on-wafer target. The methodology is explained and discussed. It is demonstrated that HMQ helps to reduce target asymmetry impact on measurement uncertainty and to select primary recipe parameters (wavelength, polarization, etc.). Finally CD-SEM measurements were used to validate methodology results.

At the 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical. We establish proof off concept for ASML’s holistic lithography hot spot detection and defect monitoring flow, process window optimizer (PPWO), for a 228nm metal layer process. We demonstrate prediction and verification of defect occurrence on wafer that arise from focus variations exceeding process window margins of device hotspots. We also estimate the improvement potential if design aware scanner control was applied.

The concept of the multi-source focus correlation method was presented in 2015 [1, 2]. A more accurate understanding of real on-product focus can be obtained by gathering information from different sectors: design, scanner short loop monitoring, scanner leveling, on-product focus and topography. This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.

On product wafers, scanner focus is better controlled at the wafer center than at the wafer edge. This is due, in a large part, to edge roll off effects [1]. This paper quantifies the impact of edge roll off on scanner levelling non-correctable errors and correlates this to on-product effects. The main contributors and mitigation methods are also discussed for a NXT:1950 scanner.

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 1, 5] show that even though the intrafield component stays the same this becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. To improve focus margin, a study has been started to determine if some correlations between scanner levelling performance, product layout and topography can be observed. Both topography and levelling intrafield fingerprints show a large systematic component that seems to be product related. In particular, scanner levelling measurement maps present a lot of similarities with the layout of the product. The present paper investigates the possibility to model the level sensor’s measured height as a function of layer design densities or perimeter data of the product. As one component of the systematics from the level sensor measurements is process induced topography due to previous deposition, etching and CMP, several layer density parameters were extracted from the GDS’s. These were combined through a multiple variable analysis (PLS: Partial Least Square regression) to determine the weighting of each layer and each parameter. Current work shows very promising results using this methodology, with description quality up to 0.8 R2 and expected prediction quality up to 0.78 Q2. Since product layout drives some intrafield focus component it is also important to be able to assess intrafield focus uniformity from post processing. This has been done through a hyper dense focus map experiment which is presented in this paper.

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 2, 5] show that even though the intrafield component stays the same, it becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. In a previous paper, the feasibility of anticipating the scanner levelling measurements (Level Sensor, Agile and Topography) has been shown [1]. This model, built using a multiple variable analysis (PLS: Partial Least Square regression) and GDS densities at different layers showed prediction capabilities of the scanner topography readings up to 0.78 Q² (the equivalent of R² for expected prediction). Using this model, care areas can be defined as parts of the field that cannot be seen nor corrected by the scanner, which can lead to local DOF shrinkage and printing issues. This paper will investigate the link between the care areas and the intrafield focus that can be seen at the wafer level, using offline topography measurements as a reference. Some improvements made on the model are also presented.