servers.This also allows many instances of the system to be started -with the number of instances only limited by the availability of general purpose computing resources.The primary challenge to re-hosting firmware is providing valid inputs for the hardware that is not implemented in the emulator.Emulators such as QEMU [6] provide the ability to emulate a variety of CPU architectures, but provide very limited support for the huge variety of peripherals (e.g., timers, UARTs, Ethernet controllers) used in commodity embedded systems.Many different approaches have been proposed to address these challenges.One approach is to implement the hardware at low-level memory mapped register interface as done in QEMU -a laborious task that does not scale well.Another approach is hardware-in-the-loop emulation [18], where accesses to peripherals are forwarded to physical hardware -which reduces its scalability.Machine learning [14] is an approach where interactions with peripherals are recorded on hardware and used to build models of peripherals.These models are then used during emulation.Another approach is to use a fuzzer [12] to provide inputs for the peripherals.Both machine learning and fuzzing peripherals limits control over the devices making them unsuitable for high fidelity emulation.A promising approach is High Level Emulation (HLE) [8], [7], [10], [11] where common abstractions within the firmware are utilized to remove the need to provide low-level support for peripherals.Both Firmadyne [7] and Costin et al. [10], [11] utilize the Linux kernel abstractions to enable re-hosting Linux based firmware.HALucinator [8] uses hardware abstraction layers provided by micro-controller manufacturers, enabling re-hosting of simple bare-metal applications.Our goal is to advance the art of re-hosting to enable answering questions about how low-level logic and vulnerabilities in Real-Time Operating Systems (RTOS) impact the larger systems in which they are a part.While we are not yet able to achieve this final end goal we report our current progress here.To achieve this goal we extend HALucinator to work with a commercial RTOS.For a more general review of re-hosting we refer the reader to [34].RTOSes aim to make the process of writing firmware for embedded systems easier.These RTOSes provide the basic constructs for a real-time system and give the developer abstract mechanisms to define system behavior.These mechanisms are often organized as layers, which hide the working details of the system from higher layers.In addition, these operating systems define an interface-called a Board Support Package (BSP)-to enable portability across a large variety of hardware.These layers, and in particular the BSP, provide a natural place for HALucinator to decouple firmware from its hardware and enable re-hosting in an emulator.Here we focus on VxWorks, a commercial RTOS Abstract-Emulating firmware is increasingly popular for systems research, particularly vulnerability research.In this paper we describe how we extend HALucinator to work with real-world systems that use the popular VxWorks RTOS.We describe the Re-hosting Support Layer (its definition and implementation) with the functions necessary to get a Schneider Electric SCADAPack 350 remote terminal unit, a Schneider Electric Modicon 340 programmable logic controller, and Hughes 9201 BGAN inmarsat terminal up and re-hosted (at least partially).We share the process and our path of performing this work over the last year, and give a retrospective approach for re-hosting other RTOSes.We provide a case study with 3 real devices, and show that we can re-host portions of the firmware and perform analyses to show the success of our approach.

System emulation and firmware re-hosting have become popular techniques to answer various security and performance related questions, such as determining whether a firmware contain security vulnerabilities or meet timing requirements when run on a specific hardware platform. While this motivation for emulation and binary analysis has previously been explored and reported, starting to either work or research in the field is difficult. To this end, we provide a comprehensive guide for the practitioner or system emulation researcher. We layout common challenges faced during firmware re-hosting, explaining successive steps and surveying common tools used to overcome these challenges. We provide classification techniques on five different axes, including emulator methods, system type, fidelity, emulator purpose, and control. These classifications and comparison criteria enable the practitioner to determine the appropriate tool for emulation. We use our classifications to categorize popular works in the field and present 28 common challenges faced when creating, emulating, and analyzing a system from obtaining firmwares to post emulation analysis.

Remarkable advancements in high-throughput gene sequencing technologies have led to an exponential growth in the number of sequenced genomes. However, unavailability of highly parallel and scalable de novo assembly algorithms have hindered biologists attempting to swiftly assemble high-quality complex genomes. Popular de Bruijn graph assemblers, such as IDBA-UD, generate high-quality assemblies by iterating over a set of k-values used in the construction of de Bruijn graphs (DBG). However, this process of sequentially iterating from small to large k-values slows down the process of assembly. In this paper, we propose ScalaDBG, which metamorphoses this sequential process, building DBGs for each distinct k-value in parallel. We develop an innovative mechanism to "patch" a higher k-valued graph with contigs generated from a lower k-valued graph. Moreover, ScalaDBG leverages multi-level parallelism, by both scaling up on all cores of a node, and scaling out to multiple nodes simultaneously. We demonstrate that ScalaDBG completes assembling the genome faster than IDBA-UD, but with similar accuracy on a variety of datasets (6.8X faster for one of the most complex genome in our dataset).

This work shows how to parallelize multi K de Bruijn graph genome assembly simultaneously, removing the bottleneck of iterative multi K assembly. The expected execution time on a single node with 40 cores is variable, with the average execution time for the entire pipeline over 16 datasets tested being 1613 s for SPAdes vs. 1581 s for MULKSG, with the MULKSG graph creation and traversal averaging 15 https://github.com/cwright7101/mulksg .

Extraordinary progress in genome sequencing technologies has led to a tremendous increase in the number of sequenced genomes. However, biologists have run into a computational bottleneck to assemble large and complex genomes quickly, due to the lack of scalable and parallel de novo assembly algorithms. Among several approaches to assembly, the iterative de Bruijn graph (DBG) assemblers, such as IDBA-UD, generate high-quality assemblies by sequentially iterating from small to large k-values used in graph construction. However, this approach is time intensive because the creation of the graphs for increasing k-values proceeds sequentially. For example, with just eight k-values, graph construction takes 96% of the total time to assemble a metagenomic dataset with 33 million paired-end reads. In this paper, we propose ScalaDBG, which transforms the sequential process of DBG construction for a range of k values, to one where each graph is built independently and in parallel. We develop a novel mechanism whereby the graph for the higher k value can be "patched" with contigs generated from the graph with the lower k value. We show that for a variety of datasets our technique can assemble complex genomes much faster than IDBA-UD (6.7X faster for the most complex genome in our dataset) while maintaining the same accuracy for the assembled genome. Moreover, ScalaDBG's multi-level parallelism allows it to simultaneously leverage the power of mighty server machines by using all their cores and of compute clusters by scaling out.

Breakthroughs in gene sequencing technologies have led to an exponential increase in the amount of genomic data. Efficient tools to rapidly process such large quantities of data are critical in the study of gene functions, diseases, evolution, and population variation. These tools are designed in an ad-hoc manner, and require extensive programmer effort to develop and optimize them. Often, such tools are written with the currently available data sizes in mind, and soon start to under perform due to the exponential growth in data. Furthermore, to obtain high-performance, these tools require parallel implementations, adding to the development complexity. This paper makes an observation that most such tools contain a recurring set of software modules, or kernels. The availability of efficient implementations of such kernels can improve programmer productivity, and provide effective scalability with growing data. To achieve this goal, the paper presents a domain-specific language, called Sarvavid, which provides these kernels as language constructs. Sarvavid comes with a compiler that performs domain-specific optimizations, which are beyond the scope of libraries and generic compilers. Furthermore, Sarvavid inherently supports exploitation of parallelism across multiple nodes. To demonstrate the efficacy of Sarvavid, we implement five well-known genomics applications---BLAST, MUMmer, E-MEM, SPAdes, and SGA---using Sarvavid. Our versions of BLAST, MUMmer, and E-MEM show a speedup of 2.4X, 2.5X, and 2.1X respectively compared to hand-optimized implementations when run on a single node, while SPAdes and SGA show the same performance as hand-written code. Moreover, Sarvavid applications scale to 1024 cores using a Hadoop backend.