A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

Controlling thermal dissipation by operating components in car batteries requires a heat management design that is of utmost importance. As a proactive cooling method, the usage of PCM (Phase Change Materials) to regulate battery module temperature is suggested. Even at lower flow rates, liquid cooling has a heat transfer coefficient that is 1.5–3 times better. The rate of global cell production has increased today from 4,000 to 100,000 cells per day. Future-proof Li (metal) battery chemistry with a 3x increase in energy density. Ineffective thermal management of the battery is the root of the issue. In order to optimise battery modules, it is important to identify likely failure modes and causes. The medium used to carry heat from the battery over its passage duration at various operating temperatures is a variety of phase-change materials. The latent heat is significant, and many vegetable fats derived from fatty acids are more effective than salt hydrates and paraffin. Melting temperatures range between -30 and 150 degrees Celsius. As a result of optimisation, the root mean square temperature between batteries was reduced by 13.3% when compared to the primary battery temperature control system. In our work, we describe techniques for enhancing temperature uniformity and cooling in a simple pack battery. Four distinct battery pack combinations are in the works. In the first concept, an intake plenum is added to a standard battery pack. In the second design, jet inlets are integrated with the inlet plenum, and multiple vortex generators are included with the inlet plenum in the third configuration. Finally, the battery pack in the fourth iteration contains an intake plenum, jet inlets, and many vortex generators. The results reveal that integrating an intake plenum, several vortex generators, and jet inlets in the same design yielded significant improvements. According to the findings, the maximum temperature of the battery pack is reduced by 5%, and the temperature differential between the greatest and lowest temperatures recorded by the battery pack is reduced by 21.5 percent.

Polar codes are the capacity-achieving error-correcting code proved to be a significant invention in coding theory. It can achieve channel capacity at infinite code length N due to its explicit code construction. However, the processing complexity along with the higher latency due to successive cancellation (SC) decoding is being a major design issue, which reduces the utilization rate in the decoder architectures. This paper presents a modified semi-parallel architecture for decoding polar code with a better decoding latency. Precomputation and look ahead techniques are used to generate two bits in the final stage. Pipelined partial-sum unit with a less critical path reduces hardware complexity independent of code length. Hence, the fact that the proposed architecture reduces the latency by 2.7 times leads to increase in utilization rate than prior semi-parallel architecture. For a code length of N = 2(10), the proposed architecture shows 62.7% and 94% improved utilization rate compared to the conventional semi-parallel architecture and 2-bit SC decoder, respectively. Compared to the conventional semi-parallel decoder for N = 2(17), hardware resource such as look-up-tables (LUT) and flip-flops (FF) usage are reduced by 98% in field programmable gate array (FPGA) leads to reduction in processing complexity. Hence, very large efficient polar decoders with a high utilization rate can be implemented in FPGA.

An unmanned aerial vehicle, commonly known as a drone, is an aircraft without a human pilot aboard. Essentially, a drone is a flying robot that can be remotely controlled or fly autonomously through software-controlled flight plans in their embedded systems, Flying robots are increasingly adopted in search and rescue missions because of their capability to quickly collect and stream information from remote and dangerous areas. Their maneuverability and hovering capabilities allow them to navigate through complex structures, inspect damaged buildings, and even explore underground tunnels and caves. Since their size is fixed, maneuvering over the compact areas and tunnels of variable size becomes an issue. To overcome this issue, we propose a model of quadrotor design which has the capability to change its size. The arm length of the quadrotor is changed dynamically so that it can fly in areas of variable sizes that would be hard to reach with the quadrotor of fixed arm length. On the other hand, our model is cost-effective, since the arm of the drone is designed with PVC (Polyvinyl Chloride). Using this model, drones will be able to move over compact areas and passages of variable sizes, thus aiding in better exploration during search and rescue operations.

This paper investigates the various pipelined FFT architectures based on radix-2, radix-2 2 & radix-2 3 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.

This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.

The current technology move towards 5G wireless standards which needs the requirement of higher data rates, low latency than the existing 4G standards. This leads to the requirement of capacity achieving channel code than the existing turbo codes/LDPC codes. Polar codes have emerged as the first provable capacity achieving error correcting codes. But inefficiency in the hardware performance of polar decoder has become the serious challenges that affect the practical usage of polar codes. This paper compares the performance of various SC decoder architecture for polar codes in terms of hardware utilized and path delay. It is studied that by decoding two bits simultaneously using 2b-SC decoder, latency can be reduced from (2n-2) to (1.5n-2) clock cycles without any degradation in performance.

Low density parity-check code (LDPC) is an error correcting code used in noisy communication channel (e.g. AWGN) to reduce the probability of error in information. By using LDPC codes, this probability can be made comparatively small, so that the data transmission rate can be as close to Shannon's limit. The decoding of Low Density Parity Check (LDPC) codes by iterative process of belief propagation gives challenges for designers looking for real time performance in communication systems. This thesis work proposes the use of Artificial Neural Networks (ANN) to replace belief propagation to approach closer to Shannon's limit more closer than other traditional decoding methods. This thesis is intended to design a new methodology to decode LDPC codes in Non-iterative manner with the help of ANN and Look Up Table (LUT). This work is at initial stage and will be extended for better performance.