The balanced comparator (BC), a pair of Josephson junctions, is a key building block and decision-making element for the rapid single flux quantum (RSFQ) logic cells. The properties of the BC define the maximum clock frequency and bit error rate of RSFQ cells and circuits. Comparators are well characterized by two parameters, the gray zone (GZ) and the gray zone threshold (GZT). Both parameters depend on the dynamic properties of a pair of junctions forming the BC and its surrounding circuitry. In addition, the gray zone depends on the thermal noise in Josephson junctions. The GZ and GZT parameters can be easily measured for various BCs and be used for model-to-hardware correlations. This makes the BC a unique circuit to validate and calibrate any Josephson simulator by comparing measured and simulated characteristics, including both dynamic and noise properties. In this article, we used a set of BCs designed for the SFQ5ee fabrication process at MIT Lincoln Laboratory to validate and calibrate the Synopsys PrimeSim HSPICE simulator. We were able to match experimental and simulated results and reproduce in simulations the main features observed experimentally and predicted theoretically. A list of recommended design variations to validate a Josephson simulator is provided.

The Josephson balanced comparator (BC) is a key component for all RSFQ/ERSFQ logic cells. Its frequency-dependent properties (gray zone and threshold current value) define the maximum clock frequency and bit error rate (BER) of RSFQ/ERSFQ circuits. The balanced comparator can also be used for various monitoring purposes. In this paper, we focus on clock sources and analyze several of them by means of BCs. We show experimentally how local overheating, associated with sub-optimally designed analog clock sources, can compromise the HF performance of a balanced comparator as well as an RFSQ/ERSFQ circuit on the same chip. We also investigate a clock source based on an external HF generator followed by an on-chip DC/SFQ converter and a frequency doubler. We use the balanced comparator's performance to optimize the on-chip part of the clock source at HF. In addition, we verify the advantage of overshunting the comparator driver to achieve higher clock frequency and lower BER. All test circuits were designed for the SFQ5ee fabrication node at MIT-LL, but conclusions can be applied to other fabrication processes.

The Josephson balanced comparator (BC) is a decision-making element and a key building block for all RSFQ logic cells. The comparator is usually characterized by two parameters: gray zone and threshold value. Both parameters depend on the comparator's design, the design of a BC's driver, as well as temperature and frequency of operation. In this paper, we focus on the high-frequency properties of the balanced comparators designed for the Nb SFQ5ee fabrication node at MIT-LL. RSFQ circuits, fabricated at this node, operate nowadays routinely at about 50 GHz. We demonstrate that a further increase of the operational frequency up to 75 GHz with a bit-error rate (BER) of 10 -14 can be achieved by optimizing the comparator's driver design. We estimate BER of 10 -3 at 100 GHz, which is not enough for complex circuits. An acceptable BER at 100 GHz requires additional optimization of design and fab.

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 −12 and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 −12 was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10 −12 with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA/2 Ω fab node.

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 −12 . We discuss future steps to improve the SB technique.

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm 2 SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

The Josephson balanced comparator, a decisionmaking circuit comprising two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured, is ubiquitous in single flux quantum (SFQ) logic. Its noise properties are crucial for the performance of logic devices. The characteristics of the balanced comparator can also be used to monitor fab process and design implementation as an indicator for excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure gray zone of various comparators fabricated in different nodes of process at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies and an analog testbed to perform high frequency characterization. Experimental results for gray zone of comparators designed for fabrication nodes with different current densities, sheet resistances, critical damping are presented and studied as a function of clock frequency.

Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.

Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums seven inputs has been designed and tested at the target clock frequency of 40 GHz and at frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output at the same target frequency was designed by combining 2 variants of 8-to-4 parallel counters. The first variant based on the 7-to-3 parallel counter, sums eight unweighted inputs, whereas the second variant sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.

Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: 1) data transmitters or output drivers with SFQ input, 2) additional amplifiers, 3) transmission lines, and 4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.

As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2 process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.

We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.

The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.

The signal-to-noise ratio (SNR) of a low-pass phase modulation-demodulation analog-to-digital converter (LP PMD ADC) depends on the number of channels in its demodulator (syn-chronizer or race arbiter). For 3, 7, and 15 channels, this gives 9.5, 16.9, and 23.5 dB theoretical SNR gain in comparison to a single channel. We have designed a family of parallel counters that sums the unweighted outputs of each synchronizer channel to produce a binary code. A 7-to-3 counter that can be truncated into 3-to-2 and extended into 15-to-4 adders was fabricated using 10 and 20 kA/cm(2) MIT-LL processes and successfully tested. The completed designs of 1-, 3-, and 7-channel LP PMD ADC are also briefly discussed.

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/ demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/ cm(2) four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/ cm(2) process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1-2 mu s to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.

We have devised a digital time-division multiplexing (TDM) scheme for minimizing the circuit complexity required for an array of sensors. As a proof-of-concept, we have designed, fabricated, and tested a four-channel digital TDM readout circuit. The proposed scheme can be generalized for a larger number of channels. The readout circuit comprises an array of ADCs to digitize sensor outputs, a multiplexing unit, a clock controller, and a counter with parallel-to-serial output interface. For demonstration purposes, we employed low-pass phase modulation-demodulation ADCs running in a synchronous mode of operation. To facilitate an independent verification of circuit operation, we also placed an on-chip pattern generator to apply a unique pattern to each channel. The multiplexing unit is based on an array of sequentially triggered switches, each controlling the flow of data from a single ADC to a common output bus. In our scheme, the switches are realized using RS-flip-flops with nondestructive (RSN) readout cells with only one RSN cell turned on at a time. Multiplexed output data were stored in ripple counter based on T-flip-flops and read out to room temperature electronics using a serial interface. The chip was immersed in liquid helium at 4.2-K temperature and extensively evaluated at sampling frequencies up to 12.8 GHz. By means of embedded pattern generators, we proved the correct operation of each channel and of all four channels combined. We also were able to perform reconstruction of a signal applied to individual ADC. The chip was fabricated using HYPRES' 4.5-kA/cm 2 process with four Nb metal layers. We briefly discuss the proposed scheme's scalability for higher current density and smaller feature size fab processes.

One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the superconductor ADC technology matures toward more complex designs for higher dynamic range performance, the need for synchronous clocking of multiple comparators continues to grow. Since high-frequency external clock sources are expensive and make a significant contribution to the heat load of the system, a high-frequency and low-jitter on-chip clock source using long Josephson junction (LJJ) is considered the preferred long-term solution. Toward that end, we are working on improving an on-chip 110-GHz clock source based on an unshunted LJJ in annular geometry. Minimizing the additional jitter added by each fan-out of the clock signal is the effort's goal. For synchronous clocking of up to three comparators, we compare clock distribution using superconducting passive transmission lines and a new approach using novel active transmission lines. We also introduce a method of synchronizing LJJ clock source with an external stable oscillator by injection locking.

A superconducting digital-RF receiver with high-ingest-rate data recording capability has been developed. The data recorder unit uses standard PC components with state-of-the-art solid-state drives (SSDs) and interfaces with the superconductor analog-to-digital converter (ADC) through a commercial FPGA board. High-speed data ingest rates exceeding 3.2 Gbps have been demonstrated successfully with single-bit ADCs clocked up to 27.52 GHz. A continuous recording of 2.5 TB has been achieved using a bank of 12 SSDs. A new graphical user interface featuring single button operation and automatic file naming, as well as convenient configuration setting, has been developed.