There is a current upsurge in research on devices with nanoparticles embedded in dielectrics. Such structures can operate as memories with high speed, high density, low voltage and low cost. Here, we report on hybrid gold nanoparticle-based metal-insulator-semiconductor (MIS) memory devices combining silicon technology and organic thin film deposition. The nanoparticles are deposited using a self-assembly technique at room temperature onto a 4.5 nm thermal silicon oxide layer. A 40 nm thin film of pentacene (deposited by flash thermal evaporation), polymethylmethacrylate (spin coated) and cadmium arachidate (deposited using the Langmuir- Blodgett technique) are used as insulators. Distinct capacitance-voltage (C-V) hysteresis is observed with a memory window that increases linearly with increasing voltage programming range. Clockwise and anticlockwise hysteresis in devices based on p-type and n-type silicon, respectively are observed, indicating that charges are injected from the top electrode to the nanoparticles rather than tunnelling through the thin SiO2 layer. However, thermal growth of SiO2 at a temperature below 800 °C resulted in a hysteresis in the opposite direction. The detailed electrical behaviour of the MIS devices will be discussed.

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on p-type silicon substrates and using polymethylmethacrylate (PMMA) as the dielectric. Gold nanoparticles, single-wall carbon nanotubes and C60, deposited at room temperature, were used as charge-storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A relatively large memory window of about 2.2 V was achieved by scanning the applied voltage of an Al/PMMA/C60/SiO2/Si structure between 4 and −4 V. Gold nanoparticle-based memory devices produced the best charge retention behaviour compared to the other MIS structures investigated.

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO2/p-Si structure between 9 and −9V.

This report discusses some of the electrical and optical properties of thin films of the organic semiconductor pentacene fabricated using thermal evaporation. Conductivities of between 1.84 × 10 Ω cm and 7.49 × 10 Ω cm are reported. Transistors using thermally evaporated pentacene were fabricated and mobilities of up to 0.03 cmVs were obtained.