The performance-limiting electron and hole trapping centers in 4H-SiC PiN power diodes are determined by combined deep-level transient Fourier spectroscopy (DLTFS) experiments and technology computer-aided design (TCAD) simulations. Two electron traps E-1 (E-C - 0.19 eV) and E-2 (E-C - 0.67 eV) and three hole traps H-1 (E-V + 0.16 eV), H-2 (E-V + 0.3 eV), and H-3 (E-V + 0.63 eV) are detected by DLTFS. Since DLTFS measurements were limited to 400 K, a few deep-level defects could not be detected in our experiments. In addition to the traps identified by DLTFS, two deep levels commonly reported at elevated temperatures, E-3 (E-C - 1.65 eV) and H-4 (E-V + 1.43 eV), are integrated into the TCAD model to perform a reliable trapping analysis. The effects of electron traps, hole traps, and individual traps are evaluated by selectively excluding them from the simulation. Hole trapping is found to be more prominent than electron trapping in pristine (as-fabricated/untouched) diodes. Among the traps, shallow hole trap H-1 exhibits a strong impact in reducing the conduction current (followed by E-3) in pristine diodes. To explore the fundamental nature of each trap, the concentration (N-T) of an individual trap is increased to a higher value without changing the N-T of other defects. Subsequently, the diode characteristics are analyzed at higher N-T of the specific trap. The traps E-2 and E-3 significantly reduce the diode current at higher N-T. The deep acceptor E-2 is primarily responsible for the donor doping compensation in the n(-) drift layer.

This work investigates the incomplete ionization effects of aluminum (Al) acceptor dopants on the static and dynamic performance of 4H‐SiC PiN power diodes, using calibrated TCAD simulations. The N dopants form shallow donor energy at E C − 0.065 eV and are nearly completely ionized at room temperature, while the Al acceptor introduces a deeper level at E V + 0.19 eV, resulting in only partial ionization. The reduced acceptor activation decreases the minority carrier injection, thereby undermining conductivity modulation. Hence, 18.4% reduction in forward current at 5 V is observed under the incomplete ionization case, relative to the complete ionization conditions. Conversely, reverse recovery performance improves due to the reduced charge storage under incomplete ionization, leading to 34.2%, 18.9%, and 29.6% reductions in reverse recovery charge ( Q rr ), current ( I prr ), and time ( T rr ), respectively. The reverse I R – V R and C–V characteristics remain unaffected by the incomplete ionization. The Al acceptor energy at E V + 0.02 eV, which yields 99% ionization, is also anticipated at room temperature. Furthermore, the temperature‐dependent ionization behavior of Al acceptors and their influences on the electrical properties are evaluated. Therefore, incomplete Al ionization‐induced deviations in the 4H‐SiC PiN diode properties are comprehensively reported.

This work presents a temperature-dependent micro-Raman spectroscopy study (300-573 K) of homoepitaxial n-type GaN layers with different Si doping levels ranging from 1015 to a few 1018 cm-3, where the analysis of different vibrational modes enables simultaneous extraction of structural and electronic properties. The evolution of the E2(high) mode and the associated phonon correlation length with doping and temperature reveal progressive lattice disorder, allowing static disorder related to dopant incorporation to be distinguished from dynamic disorder arising from phonon interactions. In parallel, the A1(LO) mode highlights the Fano interaction between the discrete phonon and the electron continuum, where the asymmetry parameter provides access to the Fermi level EF position. At 300 K, the energy separation between the conduction band and EF decreases from ∼0.19 eV for the lightly doped sample to ∼0.03 eV for the heavily doped sample. At 573 K, this distance increases to ∼0.43 eV and ∼0.08 eV, respectively, reflecting the temperature-dependent shift of the chemical potential. These results confirm both efficient dopant activation and the transition toward quasi-degenerate behavior at high carrier concentrations. Finally, analysis of A1(LO) phonon-plasmon coupling within the LPP model allows the determination of carrier mobility as a function of doping and temperature: at 300 K, the mobility decreases from 916 cm2/V·s in lightly doped samples to 355 cm2/V·s in heavily doped layers, with further reductions at elevated temperatures due to thermally activated scattering and carrier redistribution. These results demonstrate that Raman spectroscopy is a powerful nondestructive tool to simultaneously assess electronic transport properties and crystalline disorder in vertical GaN-based power electronics.

In this work, using micro-Raman spectroscopy mapping, we propose a methodology to separate the stress effect from the n-doping effect on A(1) (LO) and E-2(H) GaN phonon modes frequency for low n-doped (<1017 cm-3) GaN layers grown on various substrates (GaN, sapphire, and silicon). This methodology shows a linear relation between the two phonon modes, in which the slope corresponds to GaN biaxial stress coefficients ratio K-A1(B) ((LO))/K-E(B)H 2 and is 0.76 6 0.01. Our value may act as a useful guideline for selecting or refining K-E(B)H 2 and K-A1(B)(LO) values. Samples that are mainly biaxially stressed show good agreement with the linear relation independently of the substrate. As for GaN/GaN samples, the change of slope indicates that layers are predominantly under dislocation-induced stress. However, independently of the substrate, the y-intercept increases with the n-carrier concentration, which provides a qualitive estimation of the net doping.

TCAD simulations of the switching of power diodes are essential in the development process. Power diodes are optimized structurally to be compliant with the specifications required by the targeted applications. For silicon power diodes, carrier lifetime engineering is performed to modify the trade-off between the forward voltage drop (Vf) and the reverse recovery charges (Qrr). To precisely simulate the switching characteristics of the diode, the test circuit needs to be accurately modeled in the simulator. The industry standard for switching test circuits is the Double Pulse Test bench (DPT). It is essential to accurately model the power transistor in the test bench which is often an IGBT or a MOSFET. A finite element analysis (FEA) model of the transistor is ideal but is not necessarily available and increases simulation time drastically. This letter demonstrates that a simple analytical approach to modeling the characteristics of an IGBT is sufficient to perform mixed mode switching simulations of a lifetime engineered silicon power diodes and reduces simulation time.

In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.

Silicon bipolar power diodes require carrier lifetime engineering to reduce switching time. Platinum diffusion is the most used method to achieve lifetime reduction. Platinum diffusion in silicon is a well understood process, however, its modeling for TCAD device simulations is lacking. In this paper, we propose a new physically precise method of modeling platinum-induced defects in silicon power diodes. We show that the precision of this new method enables truly predictive simulation of silicon power diodes.

This work presents physical and electrical characterizations of low n-doped MOCVD GaN-on-sapphire layers and associated quasi-vertical Schottky Barrier Diodes (SBDs). Samples’ GaN drift layers have globally a similar quality as examined by XRD, AFM Raman spectroscopy, C-V measurements and I-V characteristics. Some crystal defects in the GaN layer are identified by Raman spectroscopy and SEM, and their effect on the electrical characteristics of the diodes is assessed. Most of the SBDs have reverse current densities at −100 V that are comparable to that of some of the best vertical GaN-on-GaN SBDs, which can be correlated to drift layers’ doping homogeneity and dislocation density.

This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.

Performance-limiting traps in high-power 4H-SiC PiN diodes (50 A, 10 kV) are detected by integrated Deep-Level Transient Fourier Spectroscopy (DLTFS) and TCAD investigations. The DLTFS reveals five prominent trap levels: EV+0.16 eV, EV+0.3 eV, EV+0.63 eV, EC – 0.19 eV and EC – 0.67 eV. Hole traps (placed at EV+ET) are found to have higher concentrations and larger capture cross-sections than electron traps at EC - ET. Before trapping inspection, simulated I-V, C-V, and reverse recovery (RR) characteristics are validated with experimental data. Another two traps EC – 1.65 eV and EV + 1.43 eV are added in the model, as they are commonly detected in 4H-SiC PiN diode. The impact of electron trapping, hole trapping, and each trap state is estimated by removing the corresponding traps in the TCAD model. The shallow-level hole trap EV+0.16 eV essentially decreases forward conduction current (resulting in reduced RR current and time), even compared with the deep-level trap EC – 1.65 eV. So, EV+0.16 eV and EC – 1.65 eV (second only) are the performance-limiting traps in the high-power 4H-SiC PiN diodes.

This article compares the impact of different freestanding GaN substrates on the material and electrical properties of Schottky diodes. Material characterization using cathodoluminescence and Raman spectroscopy was performed to analyze defects in the wafers. Randomly distributed clusters of dislocations were observed in one sample, whereas the other sample was free of such clusters. Schottky diodes were subsequently fabricated on these wafers and electrically characterized to investigate the influence of material characteristics on key device parameters, including barrier height, ideality factor, on-resistance, leakage current, and breakdown voltage. A lower barrier height, higher ideality factor, and lower breakdown voltage were observed in the sample with clusters.

A modified TCAD approach is developed for 4H-SiC junction barrier Schottky (JBS) diode by placing distinct contacts to the Schottky barrier diode (SBD) and PN junction regions. Like reality, if a common metal contact with work function is specified for top electrode, TCAD model simulates back-to-back serially connected metal/p+-type Schottky and PN junction characteristics at the PN regions. Hence, the conventional contact definition simulates only the SBD characteristics with the reduced active area, while PN junctions remain inactive. Using modified contact strategy, the simulated forward I-V is matched with the measurements, and the SBD and PN diode current components are disassociated. The peak electric field occurs at the PN junction during reverse bias; however, reverse current is entirely caused by SBD tunneling current, thereby realizing the typical JBS diode operation. Trap-assisted tunneling (TAT) current induced by omnipresent electron traps (EC – 0.19 eV, EC – 0.65 eV, and EC – 1.65 eV) in 4H-SiC is explored for JBS diodes. The reverse I-V is eventually validated using non-local tunneling model. The TCAD simulations are extended to investigate the electron trapping effects on the I-V properties with increasing trap concentrations. Consequently, the trapping-induced changes in the internal device parameters are probed to correlate with the macroscopic variation in the diode characteristics.

The forward and reverse current transport mechanisms, temperature dependence of Schottky barrier height (SBH) and ideality factor, barrier inhomogeneity analysis, and trap parameters for Schottky barrier diodes (SBDs) fabricated on 4H-SiC, GaN-on-GaN and AlGaN/GaN epitaxial substrates are reported. High SBH is identified for Ni/4H-SiC (1.31 eV) and Ti/4H-SiC (1.18 eV) SBDs with a low leakage current density of <10(-8) A cm(-2) at -200 V. Thermally stimulated capacitance detects the well-known Z(1/2) electron trap at E-C-0.65 eV in both 4H-SiC SBDs, while an additional deep-level trap at E-C-1.13 eV is found only in Ni/4H-SiC SBDs. The vertical Ni/GaN SBD exhibits a promising SBH of 0.83 eV, and two electron traps at E-C-0.18 eV and E-C-0.56 eV are identified from deep-level transient Fourier spectroscopy. A peculiar two-diode model behavior is detected at metal/GaN/AlGaN/GaN interface of high-electron mobility transistor (HEMT); the first diode (SBH-1 of 1.15 eV) exists at the standard Metal/GaN Schottky junction, whereas the second diode (SBH-2 of 0.72 eV) forms due to the energy difference between the AlGaN conduction band and the heterojunction Fermi level. The compensational Fe-doping-related buffer traps at E-C-0.5 eV and E-C-0.6 eV are determined in the AlGaN/GaN HEMT, through the drain current transient spectroscopy experiments.

The study consists in analyzing the robustness of 650 V GaN HEMT components in case of shortcircuits. The objective is to develop a test bench for repetitive short-circuits to a component. Electrical characterizations will be carried out before and after the short-circuit cycles to identify the possible parameters drift of the tested devices, to identify the failure mechanisms. Parametric variations have been observed.

This paper presents micro-OBIC measurements performed at different biasing on two power devices protected by a combination of P + rings embedded in a JTE Zone. Thanks to the micro-OBIC micrometer spatial resolution, small gaps can be visible on OBIC profiles. Thus, the spatial variation of the micro-OBIC signal accurately reflects the topology of the periphery protection: combination of JTE and rings and channel stopper. These measurements agree with the electric field distribution (calculated by finite element method) along the structure.

New and original medium power multi-terminal SiC monolithic converter architectures are investigated with vertical switching cells based on SiC JBS diodes and VDMOS transistors. 2D TCAD and mixed-mode Sentaurus™ simulations are performed to optimize switching structures as Buck, Boost, H-bridge high-side row chip common drain-type and low-side row chip common source-type. The proper operation in the turn-on and turn-off of each cell is also studied and validated. To fabricate these new monolithic integrated architectures, two main technological bricks have been developed, for vertical insulation and the integration of a top Ni metal via. To achieve the vertical insulation deep trenches are necessary combining dry plasma and wet KOH electrochemical etching through the thick N+ substrate.

In this paper, a first demonstration of the optical triggering of a 10 kV 4H-SiC Bipolar Junction Transistor is reported. A laser emitting UV (349 nm) has been used for the generation electron-hole pairs within the device. A current density of about 20 A.cm -2 has been obtained. This low value in comparison with 100 A.cm -2 for “conventional” BJT is due to the narrow pulse width (5 ns). The current waveform shows the effect of the carrier lifetime in the base and collector regions. From these measurements, we have extracted the I C (V CE ) characteristics for different laser optical power and the switch-on time which is about 1 µs.

Wide-bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), and diamond (C), have proven to outperform traditional silicon (Si) based power electronic devices. However, the peripheral protection of these wide-bandgap devices requires careful design to handle high voltage effectively. This article highlights the potential of using the Optical Beam Induced Current (OBIC) technique to analyze the effectiveness of different protection methods and provide valuable feedback to device designers regarding peripheral termination efficiency. Designers need simulations representative of the measurement, In this article a finite element simulation is used to determine the induced current as a function of the position of the optical beam.Firstly a theoretical approach will be presented to introduce the OBIC method. Subsequently, the electro-optical characterization technique is applied to a PiN diode protected by narrow field rings.The article also showcases new results obtained from components with new-generation peripheral protection, demonstrating the continuous progress in this field.Overall, this article highlights the significance of the OBIC technique in evaluating the effectiveness of peripheral protection methods for wide-bandgap semiconductors, particularly SiC devices. By providing valuable insights into the electric field's spatial distribution, this technique aids in optimizing device design and improving overall performance. Finite element simulations in relation to the characteristics of the UV beam and its scanning across the surface of the component help to assess the geometric parameter impact on the electrical results.