Quantum computers require fast and accurate methods for qubit state detection. Phase-transition sensors exploit the abrupt change between two physical states of a material to achieve enhanced sensitivity and have enabled advanced detectors for quantum technologies, such as superconducting nanowire single-photon detectors. However, this sensing principle has not yet been applied to semiconductor spin qubits. Here, we demonstrate a superconducting phase-transition radio-frequency single-electron transistor (PTSET), a charge sensor for semiconductor spin qubits whose response is enhanced by a superconducting-to-normal phase transition. The transition is engineered by linking the sensor current to a low-critical-current, high-kinetic-inductance inductor integrated into the radio-frequency matching network. We demonstrate improvements in sensitivity of one and two orders of magnitude over conventional rfSETs in the large- and small-signal regimes, respectively. Our results establish phase-transition sensing as a route towards ultrasensitive, integrated charge sensors for semiconductor quantum computing and point to broader applications, including cryogenic photon detection for radio astronomy.

Semiconductor quantum dots (QDs) are key building blocks for quantum technologies with applications in quantum computation, communication, and sensing. QD device architectures rooted in conventional solid-state device fabrication paradigms are grappled with complex protocols to balance ease of realization, scalability, and transport properties. Using ion gating, we demonstrate a novel paradigm of quantum device engineering, that enables the realization and control of the iontronic QD. Clear Coulomb blockade peaks and their dependence on an externally applied magnetic field are reported, together with the impact of device architecture and confinement potential on QD quality. Devices incorporating two identical iontronic QDs in series are realized, addressing the reproducibility of the approach. A novel class of zero-dimensional quantum devices, iontronic QDs, overcome the need for thin dielectric layers, facilitating single-step device fabrication. This approach holds the potential to impact the development of quantum materials and devices in the context of solid-state quantum technologies.

As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots can potentially address these challenges given their control fidelities and potential for compatibility with large-scale integration. Here we report the integration of 1,024 independent silicon quantum dot devices with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, allowing characteristic data across the quantum dot array to be acquired and analysed in under 10 min. This is achieved by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, characterized by a typical signal-to-noise voltage ratio in excess of 75 for an integration time of 3.18 μs. We extract key quantum dot parameters by automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room-temperature transistor behaviour that could be used as a proxy for in-line process monitoring. The integration of 1,024 independent silicon quantum dot devices with on-chip digital and analogue electronics, all of which operate below 1 K, allows characteristic data across the quantum dot array to be acquired and analysed in under 10 min.

Integrated photonics on Silicon-On-Insulator (SOI) substrates is a well developed research field that has already significantly impacted various fields, such as quantum computing, micro sensing devices, biosensing, and high-rate communications. Although quite complex circuits can be made with such technology, everything is based on a few ’building blocks’ which are then combined to form more complex circuits. This review article provides a detailed examination of the state of the art of integrated photonic building blocks focusing on passive elements, covering fundamental principles and design methodologies. Key components discussed include waveguides, fiber-to-chip couplers, edges and gratings, phase shifters, splitters and switches (including y-branch, MMI, and directional couplers), as well as subwavelength grating structures and ring resonators. Additionally, this review addresses challenges and future prospects in advancing integrated photonic circuits on SOI platforms, focusing on scalability, power efficiency, and fabrication issues. The objective of this review is to equip researchers and engineers in the field with a comprehensive understanding of the current landscape and future trajectories of integrated photonic components on SOI substrates with a 220 nm thick device layer of intrinsic silicon.

InAs nanowire-based back-gated field-effect transistors realized starting from individual InAs nanowires are investigated at different temperatures and as building blocks of inverter circuits for logic applications. The nanodevices show n-type behavior with a carrier concentration up to 8.0 x 1017 cm-3 and corresponding electron mobility exceeding 1590 and 1940 cm2 V-1 s-1 at room temperature and 200 K, respectively. The investigation over a wide temperature range indicates no Schottky barrier at source/drain electrodes, where Ohmic contacts are formed with the Cr adhesion layer. The switching characteristics of the devices improve with decreasing temperature and a subthreshold swing less than 1 V/decade is achieved at 200 K, suggesting the occurrence of a trap population with density around 4 x 108 cm-1 eV-1. Besides, the nanodevices are exploited in single-transistor circuits with a resistive load. As an inverter, the circuit shows 30 % and 24 % of the voltage supply noise margins for the high and low states, respectively; as a low signal amplifier, it shows a gain that is weakly dependent on temperature. The present study highlights the impact of temperature on the operation of InAs nanowire-based back-gated transistors and evidences their potential applications in logic circuits including inverters and low-signal amplifiers.

Iontronics exploits mobile ions within electrolytes to control the electronic properties of materials and devices' electrical and optical response. In this frame, ionic liquids are widely exploited for the gating of semiconducting nanostructure devices, offering superior performance compared to conventional dielectric gating. In this work, we engineer ionic liquid gated InAs nanowire-based field effect transistors and adopt the set-and-freeze dual gate device operation to probe the nanowires in several ionic gate regimes. We exploit standard back-gating at 150 K, when the ionic liquid is frozen and any crosstalk between the ionic gate and the back gate is ruled out. We demonstrate that the liquid gate polarization has a persistent effect on the nanowire properties. This effect can be conveniently exploited to fine-tune the properties of the nanowires and enable new device functionalities. Specifically, we correlate the modification of the ionic environment around the nanowire to the transistor threshold voltage and hysteresis, on/off ratio and current level retention times. Based on this, we demonstrate memory operations of the nanowire field effect transistors. Our work shines a new light on the interaction between electrolytes and semiconducting nanostructures, providing useful insights for future applications of nanodevice iontronics.

Achieving stable, high-quality quantum dots has proven challenging within device architectures rooted in conventional solid-state device fabrication paradigms. In fact, these are grappled with complex protocols in order to balance ease of realization, scalability, and quantum transport properties. Here, we demonstrate a novel paradigm of semiconductor quantum dot engineering by exploiting ion gating. Our approach is found to enable the realization and control of a novel quantum dot system: the iontronic quantum dot. Clear Coulomb blockade peaks and their dependence on an externally applied magnetic field are reported, together with the impact of device architecture and confinement potential on quantum dot quality. Devices incorporating two identical quantum dots in series are realized, addressing the reproducibility of the developed approach. The iontronic quantum dot represents a novel class of zero-dimensional quantum devices engineered to overcome the need for thin dielectric layers, facilitating single-step device fabrication. Overall, the reported approach holds the potential to revolutionize the development of functional quantum materials and devices, driving rapid progress in solid state quantum technologies

Integrated photonic platforms have rapidly emerged as highly promising and extensively investigated systems for advancing classical and quantum information technologies, since their ability to seamlessly integrate photonic components within the telecommunication band with existing silicon-based industrial processes offers significant advantages. However, despite this integration facilitating the development of novel devices, fostering fast and reliable communication protocols and the manipulation of quantum information, traditional integrated silicon photonics faces inherent physical limitations that necessitate a challenging trade-off between device efficiency and spatial footprint. To address this issue, researchers are focusing on the integration of nanoscale materials into photonic platforms, offering a novel approach to enhance device performance while reducing spatial requirements. These developments are of paramount importance in both classical and quantum information technologies, potentially revolutionizing the industry. In this review, we explore the latest endeavors in hybrid photonic platforms leveraging the combination of integrated silicon photonic platforms and nanoscale materials, allowing for the unlocking of increased device efficiency and compact form factors. Finally, we provide insights into future developments and the evolving landscape of hybrid integrated photonic nanomaterial platforms.

Single-photon sources are important for integrated photonics and quantum technologies, and can be used in quantum key distribution, quantum computing, and sensing. Color centers in the solid state are a promising candidate for the development of the next generation of single-photon sources integrated in quantum photonics devices. They are point defects in a crystal lattice that absorb and emit light at given wavelengths and can emit single photons with high efficiency. The landscape of color centers has changed abruptly in recent years, with the identification of a wider set of color centers and the emergence of new solid-state platforms for room-temperature single-photon generation. This review discusses the emerging material platforms hosting single-photon-emitting color centers, with an emphasis on their potential for the development of integrated optical circuits for quantum photonics.

Innovative silicon photonic-based polarization converting device can be realized with the integration of semiconducting InP nanowires (NWs) on the silicon photonic platform. We have recently designed a compact polarization converter and demonstrated its full performances (from quasi-TE modes to quasi-TM modes, and vice versa): see talk “Semiconductor NW’s for polarization control in integrated silicon on insulator waveguides” at this conference and [1].

Electrical control of material properties is a fundamental tool exploited by scientists and engineers to deploy devices and investigate fundamental phenomena. However, “conventional” gating techniques based on oxides often limits device performance for many electronic applications [1] . On the other hand, Ion-gating [2] , replacing the dielectric with an electrolyte featuring high ionic mobility, offers a new solution to link electronics and ionics, leading to exceptional results in both fundamental theoretical studies of solid-sate physics [3] as well as practical applications. However, Despite the widespread success achieved by this performing technique, some information is still missing regarding the optimal device geometry and architecture to be developed in order to maximize the ionic concentration at the electrolyte/semiconductor interface to provide enhanced device operation.

Since the 1980s, researchers have taken giant steps in understanding how to use quantum mechanics for solving real problems—for example, making a computer that works according to the laws of quantum mechanics. In recent decades, researchers have tried to develop a platform for quantum information and computation that can be integrated into digital and telecom technologies without the need of a cryogenic environment. The current status of research in the field of quantum integrated photonics will be reviewed. A review of the most common integrated photonic platforms will be given, together with the main achievements and results in the last decade.

The study of two-dimensional (2D) materials has gained significant attention due to their potential use in electronic, spintronic, and optoelectronics applications. Transition metal dichalcogenides (TMDs)[1], a type of 2D material, are particularly interesting because they have a bandgap that changes from indirect to direct as their thickness decreases from bulk to monolayer[2]. Tungsten disulphide (WS 2 )[3] is of particular interest due to its direct bandgap in the visible range, making it suitable for electronics and optoelectronics applications. Therefore, it is important to control the growth process to obtain high-quality WS 2 with desirable electronic and optical properties using chemical vapor deposition (CVD) growth for mass production of commercial devices.

Quantum computers are nearing the thousand qubit mark, with the current focus on scaling to improve computational performance. As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots are poised to address these challenges with their proven control fidelities and potential for compatibility with large-scale integration. Here, we demonstrate the integration of 1024 silicon quantum dots with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, enabling characteristic data across the quantum dot array to be acquired in just 5 minutes. We achieve this by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, reaching a minimum integration time of 160 ps. Key quantum dot parameters are extracted by fast automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room temperature transistor behaviour that may be used as a proxy for in-line process monitoring. Our results show how rapid large-scale studies of silicon quantum devices can be performed at lower temperatures and measurement rates orders of magnitude faster than current probing techniques, and form a platform for the future on-chip addressing of large scale qubit arrays.

The increasing energy demand and the ever more pressing need for clean technologies of energy conversion pose one of the most urgent and complicated issues of our age. Thermoelectricity, namely the direct conversion of waste heat into electricity, is a promising technique based on a long-standing physical phenomenon, which still has not fully developed its potential, mainly due to the low efficiency of the process. In order to improve the thermoelectric performance, a huge effort is being made by physicists, materials scientists and engineers, with the primary aims of better understanding the fundamental issues ruling the improvement of the thermoelectric figure of merit, and finally building the most efficient thermoelectric devices. In this Roadmap an overview is given about the most recent experimental and computational results obtained within the Italian research community on the optimization of composition and morphology of some thermoelectric materials, as well as on the design of thermoelectric and hybrid thermoelectric/photovoltaic devices.

Conventional techniques of measuring thermal transport properties may be unreliable or unwieldy when applied to nanostructures. However, a simple, all-electrical technique is available for all samples featuring high-aspect-ratio: the 3ωmethod. Nonetheless, its usual formulation relies on simple analytical results which may break down in real experimental conditions. In this work we clarify these limits and quantify them via adimensional numbers and present a more accurate, numerical solution to the 3ωproblem based on the Finite Element Method (FEM). Finally, we present a comparison of the two methods on experimental datasets from InAsSb nanostructures with different thermal transport properties, to stress the crucial need of a FEM counterpart to 3ωmeasurements in nanostructures with low thermal conductivity.

Thermoelectric polyelectrolytes are emerging as ideal material platform for self-powered bio-compatible electronic devices and sensors. However, despite the nanoscale nature of the ionic thermodiffusion processes underlying thermoelectric efficiency boost in polyelectrolytes, to date no evidence for direct probing of ionic diffusion on its relevant length and time scale has been reported. This gap is bridged by developing heat-driven hybrid nanotransistors based on InAs nanowires embedded in thermally biased Na+ -functionalized (poly)ethyleneoxide, where the semiconducting nanostructure acts as a nanoscale probe sensitive to the local arrangement of the ionic species. The impact of ionic thermoelectric gating on the nanodevice electrical response is addressed, investigating the effect of device architecture, bias configuration and frequency of the heat stimulus, and inferring optimal conditions for the heat-driven nanotransistor operation. Microscopic quantities of the polyelectrolyte such as the ionic diffusion coefficient are extracted from the analysis of hysteretic behaviors rising in the nanodevices. The reported experimental platform enables simultaneously the ionic thermodiffusion and nanoscale resolution, providing a framework for direct estimation of polyelectrolytes microscopic parameters. This may open new routes for heat-driven nanoelectronic applications and boost the rational design of next-generation polymer-based thermoelectric materials.

We report the fabrication, electrical characterization, and digital applications of back-gated field-effect transistors with a single InAs nanowire as the conductive channel. The devices show n-type conduction with a field-effect mobility higher than 550 c$\mathrm{m}^{2}\mathrm{V}^{-1}\mathrm{s}^{-1}$ at room temperature. The transfer characteristics exhibit hysteresis width that increases with increasing temperature. The temperature dependence of the electrical properties of InAs nanowires is investigated in the range from 290 to 340 K. The InAs nanowire transistors are exploited for nonvolatile memories and implemented in resistive-load circuits that operate as inverters. Our results are promising for the practical applications of InAs nanowires in the wide field of digital electronics.

Graphene can be used to fabricate hybrid photonic nanodevices for the coherent and dynamically control photon polarization in photonic waveguides. In these nanodevices the graphene conductivity regime can be precisely tuned by modifying the Fermi level with a gate voltage, moving in a regime where the inter-band chiral transitions, rather than the surface plasmon polariton, dominate the optical polarization. We exploit this property to design integrated Graphene/Silicon quantum photonics waveguides with polarization control, performing a numerical investigation of the use of graphene nanoribbons placed on top of a silicon-on insulator (SOI). These devices are intended for they implementation in silicon photonics polarization-encoded Quantum Key Distribution (QKD) systems working in the telecom C-band, exploiting the advantage of the Si based technology as regards cost, scalability, power consumption and reliability. Graphene can selectively sustain both TE and TM polarization modes, depending on the energies of the photon energy and on the graphene chemical potential of graphene, with a broadband operation due to its gapless optical spectrum. We found that two factors mainly determine the polarization control: (i) the graphene chemical potential and (ii) the geometrical parameters of the waveguide, such as the waveguide and nanoribbon widths and distance. We revealed that the graphene chemical potential influences both TE and TM polarizations in a similar manner, and that the use of a tapered waveguide allows both TE-pass and TM-pass polarizing functionalities. The increase of the the thickness of an oxide spacer placed between the Si waveguide and the graphene nanoribbon allows a reduction of the device insertion losses, while maintaining preserving high polarization extinction ratio. Our numerical analysis show that the tuning of the chemical potential affects the TE and TM polarizations in similar way but induces different optical losses. We found that that the tuning of the chemical potential at energy above 0.5 eV leads to a remarkable reduction of the losses to reduce the optical losses. We also found that increasing the thickness of the oxide spacer the device insertion losses are reduced, keeping a a reasonably low polarization extinction ratio.

The search for new and more sustainable ways of producing energy has led to the study of novel thermoelectric materials featuring high efficiency in the direct conversion of waste heat into electricity, for which novel materials are required to exhibit low thermal conductivity coupled with high electrical conductivity [1] . In this scenario, incommensurate chimney-ladder compounds [2] (e.g., SnCr 2 S 4 ) can be identified as a promising material class, owing to the expectations for their ultra-low thermal conductivity. However, to date their electric transport properties remain unveiled.