An edge-based finite element formulation with conformal absorbing boundary conditions (ABCs) is presented for scattering by composite three dimensional structures having boundaries satisfying impedance and/or transition conditions. The methodology with its O(N) storage requirement is amenable to large-scale parallelization. Tests have been carried out on a massively parallel architecture with impressive speedups

The finite element method (FEM) with local absorbing boundary conditions has been recently applied to compute electromagnetic scattering from large 3-D geometries. In this paper, we present details pertaining to code implementation and optimization. Various types of sparse matrix storage schemes are discussed and their performance is examined in terms of vectorization and net storage requirements. The system of linear equations is solved using a preconditioned biconjugate gradient (BCG) algorithm and a fairly detailed study of existing point and block preconditioners (diagonal and incomplete LU) is carried out. A modified ILU preconditioning scheme is also introduced which works better than the traditional version for our matrix systems. The parallelization of the iterative sparse solver and the matrix generation/assembly as implemented on the KSR1 multiprocessor is described and the interprocessor communication patterns are analysed in detail. Near-linear speed-up is obtained for both the iterative solver and the matrix generation/assembly phases. Results are presented for a problem having 224,476 unknowns and validated by comparison with measured data.

The authors present the implementation details of a FE-ABC (finite-element absorbing boundary condition) code and describe the numerical considerations involved in optimizing this code. The linear equation solver and the sparse matrix generation were parallelized on the KSR1 (Kendall Square Research) shared-address space distributed-cache architecture with substantial speedup. Benchmarking was also done on the CM-5 (Connection Machine) with encouraging results. The parallel version of the FE-ABC code was run for a 1.5/spl lambda/ /spl times/ 1/spl lambda/ /spl times/ 1/spl lambda/ pec inlet and the monostatic radar cross section compared with measured data for HH-polarization.<>

This paper presents a behavioral characterization methodology highlighting the effects of fine-grain par-allelism features and memory hierarchies in scalar uniprocessors. This method is illustrated on a decou-pled/access execute (DAE) architecture, the Astronau-tics ZS-1. DAE architectures are hard to analyze due to the complexity of their organization and provide an interesting target for a performance analysis study. However , our method is general and could be extended to the IBM RISC RS/6000 processor as well as othe~ su-perscalar processors. 1 Introduction and motivations Current scalar architectures rely heavily on instruction-level parallelism to achieve ever higher performance. Processors which provide independent functional units for computation, memory accesses and control, allow several operations to execute concurrently. However, to exploit this capability, parallelism must be detected in the code and matched to the fine-grain parallelism available in the machine. This requires the ability to schedule and synchronize the concurrent operations in order to maintain the semantics of the code and make efficient use of the machine resources. High-performance architectures differ in the way hardware and software cooperate in the management of fine-grain parallelism. Permission to copy without fee all or pert of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice IS given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. 1 In the case of VLIW (Very Long Instruction Word) architectures, the activity of each functional unit is controlled on a cycle-by-cycle basis through a dedicated field in the instruction word. This synchronous control scheme requires advanced compiler technology to detect and schedule the concurrent activities. The code generated by the compiler needs to be free of both resource conflicts and data hazards. At the other extreme, the IBM 360/91 provides extensive , though costly, hardware support to extract instruction-level parallelism at run-time and control the asynchronous execution of the independent functional units. The Tomasulo algorithm achieves dynamic im struction scheduling by allowing instructions to execute out-of-order, thus relieving the compiler from the task of instruction scheduling. Decoupled access/execute architectures make a different trade-off and provide only a restricted run-time instruction reordering capability. DAE architectures [6, 7] consist typically of two processors, one for address gem eration and one for floating-point computations. The processors …

The techniques of “load/store” memory reference modeling is based on deriving performance characteristics of the memory architecture of a computer by looking at the behavior of simple sequences of load, store and nop (null operation) instructions. The resulting data base can be used to match load/store templates against algorithm kernels to predict performance or as a source of data for testing analytical models of the architecture. In this paper we study the BBN GP1000 parallel processing system. We show how to build a subset of the load/store kernels needed to characterize the machine and illustrate the behavior of a simple model based on the data.