This article describes the development of the Tristan 10 M detector for time-resolved synchrotron experiments. Tristan 10 M has an unprecedented time resolution (ns time scale) over long-duration continuous acquisition (days). The detector is constructed from an array of 160 Timepix3 readout application-specified integrated circuit (ASIC; about 10 million pixels) flip chip bonded to ten monolithic silicon sensors, which enable it to cover an area large enough to effectively carry out crystallography experiments. The large array of ASICs resulted in a number of severe technical challenges that had to be overcome during the development of the detector. The minimization of the dead area between sensors required the development of a very challenging mechanical and electronic packaging. Such a packaging had to be able to route the large number of data and power lines within the footprint of a sensor, had to effectively sink the heat generated by the ASICs, and had to be able to position the sensors accurately. In addition, the packaging of the detector was designed to be scalable in consideration of possible future larger versions of this detector, which added a further challenge. The data-driven nature of Timepix3 and the sheer data volume produced by the array of ASICs required us to devise a dedicated hardware, firmware, and software data acquisition architecture. This architecture proved very effective during the commissioning of Tristan 10 M when time-resolved crystallography experiments were carried out.

Pixel radiation detectors for X-rays and gammarays are commonly built by hybridization of sensor and readout application-specific integrated circuit (ASIC) chips using flip-chip bonding. A typical example is pixelated high-Z semiconductor sensor material (e.g. CdTe) bonded to a matching pixel array on an ASIC to form a hybrid module. Conventionally, the I/O connections of the ASIC for such hybrids are wire bonded to a Printed Circuit Board (PCB) which subsequently is connected to a data acquisition system. The wire bond pads and PCB connections require a considerable amount of the module's footprint and usually protrude at one side of the detector module by approximately 1.5mm. The disadvantage of this practice is that those modules are only suitable for close proximity tiling modules along three sides of the detector (3-side buttable) to form larger sensor areas. In recent years Through-Silicon Via (TSV) technology was introduced to overcome this disadvantage which permits the fabrication of potentially 4-side buttable modules. Commonly a TSV-last process step in the ASIC production is integrated. However, ASICs with TSV are expensive and the TSV-last process step is prone to failure of the TSV metallization. The consequences of the latter are missing I/O connections. Alternatively, 4-side buttable hybrid detector modules can be fabricated using interposers as pitch convertors. Here the sensor has a larger pixel-pitch than the ASIC and therefore the sensor covers a larger area than the ASIC. A Re-Distribution-Layer (RDL) on the interposer facilitates connections to the I/O of the ASIC. Therefore, ASIC and all other wire bonded connections can be placed under the sensor with all four sides of the sensor being the boundary of the full-sized module. This was demonstrated in the past with a conversion from 250um-pitch on the ASIC to a 500um-pitch on the sensor using a layered PCB. In order to achieve detectors with smaller sensor pixel pitch, the layout of pitch re-routing on the interposer has to be considerably reduced in size. As a consequence, the fabrication of such interposers becomes more difficult. This paper studies desirable designs and interposer materials and compares these with the limitations of current fine-pitch interposer fabrication methods and design rules for a pitch convertor interposer. In addition, the paper will also present necessary changes such as indium deposition on individual sensor die instead of wafer-level fabrication that have to be taken into consideration for sensor/ASIC hybridization of fine-pitch radiation detectors.

Daresbury Laboratory (DL) and Rutherford Appleton Laboratory (RAL) have developed and built radiation detectors for experiments in particle physics since decades. This includes tracker detectors which record the pathway of high energy particles in order to locate the vertexes of decay processes. These tracker detectors need to have low material budget in order to minimize scattering. The most advanced systems comprise thin CMOS sensors (approx. $100 \mu \mathrm{m}$ thick) which require interconnection to a thin (approx. $150 \mu \mathrm{m})$ Flexible Printed Circuit (FPC) board which is in turn electrically connected to the data acquisition system. The thickness of detector components and flexibility of the FPC board create challenges for the assembly of these detectors. For detectors described here, an array of 2x2 CMOS sensor chips (each 30mm x 15mm) is mounted onto an FPC creating a module. The chips are positioned in close proximity to each other (approx. $150 \mu \mathrm{m}$ gap). This paper investigates flip-chip bonding to assemble and interconnect these modules as an alternative to the standard wire bonding technique used in particle physics. For this purpose, two different methods are compared.Method 1: This is considered as the standard method where CMOS sensors are initially bonded to the FPC board with adhesive and subsequently their contact pads are wire bonded to the FPC through large via.Method 2: This is an alternative technique explored in this work where an electrically conductive adhesive is initially printed onto contact pads of the FPC and CMOS sensors are subsequently flip-chip bonded with high precision alignment to the FPC. Prior to this, contact pads on the CMOS sensor are fitted with gold studs.Reported here are considerations on the advantages and disadvantages of the proposed method 2 with respect to the standard method 1. This includes bond yield, mechanical stability of the detector module (adhesion of sensors to FPC), and complexity of the process.

In recent years multi-layered Flexible Printed Circuit (FPC) boards have advanced considerably in complexity, allowing versatile designs for electronic packaging applications which require interconnect through-via [1]. This makes these boards also attractive for interposers (pitch-convertors) in X-ray detector applications where pixelated sensors are connected to readout Application-Specific Integrated Circuits (ASIC) in order to match different pixel-pitches between sensor and ASIC. Thin boards with total thickness of approx. 140μm are also available and desirable for low radiation absorption of detector packaging in high-energy particle experiments (e.g. CMOS imaging sensor for particle tracker [2,3]). These X-ray detector sensors and ASIC are based on a wide range of materials (Si, Cd(Zn)Te, GaAs). The mismatch in thermal expansion of these different materials is a major challenge. Bonding of sensors and ASIC to flexible boards increases the risk of distortion of the assembly, with potential delamination of components from the board. The paper describes the bonding processes. Stencil printing is used to form an array of dots from electrically conductive adhesive on the sensor, interposer or FPC. ASIC and interposer board are studded with a similar array of gold studs using a ball bonding technique. Subsequently flip-chip bonding is used to bond a studded component to an array of adhesive dots on the printed counterpart. Optimal bonding parameters are evaluated using shear testing and analysis of contact area. The flatness of boards is analysed. Bonded devices are tested for their electronic functionality as X-ray detectors.