The use of annular MOSFET design, which has demonstrated total-dose radiation immunity in CMOS circuits, can improve the hot-carrier reliability of CMOS circuits by reducing the drain electric field compared to conventionally designed MOSFETs. A theoretical analysis of the annular n-MOSFET in saturation verifies the reduction of the drain electric field in properly designed MOSFETs. Hot-carrier data for an enclosed 0.25-/spl mu/m n-MOSFET demonstrate an improvement in hot-carrier lifetime by more than 3x compared to a conventional device in the same technology.

We report the thresholds for laser-induced latchup on epitaxial CMOS test structures for 600 nm and 815 nm excitation. We analyze the differences observed in terms of different latchup triggering mechanisms and compare the results with measurements of energetic particle-induced latchup.

The geometric component of charge pumping current-was examined in n-channel metal-oxide-silicon field effect transistors (MOSFETs) following low-temperature irradiation. In addition to the usual dependencies on channel length and gate bias transition time, the geometric component was found to increase with radiation-induced oxide-trapped charge density and decreasing temperature. A postirradiation injection of electrons into the gate oxide reduces the geometric component along with the density of oxide-trapped charge, which clearly demonstrates that the two are correlated. A fit of the injection data to a first-order model for trapping kinetics indicates that the electron trapping occurs predominantly at a single type of Coulomb-attractive trap site. The geometric component results primarily from the bulk recombination of channel electrons that fail to transport to the source or drain during the transition from inversion to accumulation. The radiation response of these transistors suggests that Coulomb scattering by oxide-trapped charge increases the bulk recombination at low temperatures by impeding electron transport. These results imply that the geometric component must be properly accounted for when charge pumping irradiated n-channel MOSFETs at low temperatures.

MOSFETs fabricated in the commercial American Microsystems Inc. (AMI) 0.35-/spl mu/m CMOS process were characterized with respect to the effects of total dose irradiation. Gate oxide threshold voltage shifts up to 300 krad(Si) for both NMOS and PMOS transistors biased for worst-case shifts were less than 25 mV. Off-state field leakage currents for isolated NMOS transistors was above 1 nA at 30 krad(Si). The effect of a post-irradiation high temperature anneal was to lower these leakage currents to their preirradiation levels. PMOS transistors exhibited less than 10 pA leakage for doses up to 300 krad(Si). Measurements on edgeless annular NMOS transistors showed only minor increases in leakage current with total dose up to 300 krad(Si), indicating that the increased leakage observed in standard NMOS transistors is the result of field leakage associated with inversion in the bird's beak region at the transistor/field oxide interface. Measurements of the threshold voltage, transconductance and subthreshold swing for the edgeless transistors indicated no significant changes up to 300 krad(Si), indicative of a lack of trapped holes and lack of interface state formation in the gate oxide. Measurements on ring-oscillators biased dynamically during irradiation showed less than a 5% change in gate delay and in power up to 300 krad(Si) total dose, suggesting that for actual digital circuits applications, functionality and performance may be maintained to doses substantially above 30 krad(Si).

MOSFETs fabricated in the commercial Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-mum CMOS process were characterized with respect to the effects of total dose irradiation. Gate oxide threshold voltage shifts at 70 krad(Si) for both minimum geometry 0.70 mum/0.35 un NMOS and PMOS transistors biased for worst-case shifts were less than 70 mV. Off-state field leakage currents for isolated NMOS transistors were near 1 pA at 50 krad(Si), but became large at 100 krad(Si). The effect of a post-irradiation high temperature anneal was to lower these leakage currents to less than 10 pA. PMOS transistors exhibited less than 10 pA leakage for doses up to 150 krad(Si). Measurements on edgeless annular NMOS transistors showed only minor increases in leakage current with total dose up to 2 Mrad(Si), indicating that the increased leakage observed in standard NMOS transistors is the result of field leakage associated with inversion in the bird's beak region at the transistor/field oxide interface. Measurements on field-oxide transistor test structures biased for worst-case threshold voltage shifts showed the transistors inverted between 25 and 50 krad(Si) for 3.3 V operation. Measurements on ring-oscillators biased dynamically during irradiation showed less than a 10% change in gate delay and in power up to 2 Mrad(Si) total dose, suggesting that for actual digital circuits applications, functionality and performance may be able to be maintained to doses substantially above 50 krad(Si) with the application of hardness-by-design techniques to mitigate field-oxide inversion.

An independent assessment team (IAT) was formed and met on April 2, 2001, at Lockheed Martin in Denver, Colorado, to aid in understanding a technical issue for the Mars Odyssey spacecraft scheduled for launch on April 7, 2001. An RP1280A field-programmable gate array (FPGA) from a lot of parts common to the SIRTF, Odyssey, and Genesis missions had failed on a SIRTF printed circuit board. A second FPGA from an earlier Odyssey circuit board was also known to have failed and was also included in the analysis by the IAT. Observations indicated an abnormally high failure rate for flight RP1280A devices (the first flight lot produced using this flow) at Lockheed Martin and the causes of these failures were not determined. Standard failure analysis techniques were applied to these parts, however, additional diagnostic techniques unique for devices of this class were not used, and the parts were prematurely submitted to a destructive physical analysis, making a determination of the root cause of failure difficult. Any of several potential failure scenarios may have caused these failures, including electrostatic discharge, electrical overstress, manufacturing defects, board design errors, board manufacturing errors, FPGA design errors, or programmer errors. Several of these mechanisms would have relatively benign consequences for disposition of the parts currently installed on boards in the Odyssey spacecraft if established as the root cause of failure. However, other potential failure mechanisms could have more dire consequences. As there is no simple way to determine the likely failure mechanisms with reasonable confidence before Odyssey launch, it is not possible for the IAT to recommend a disposition for the other parts on boards in the Odyssey spacecraft based on sound engineering principles.

Radiation-hard ASIC design is enabled by the trend in commercial microelectronics toward increased radiation hardness, demonstrated here with new radiation results on a 0.25-mum commercial process utilizing shallow trench isolation. A design comparison is made between creating ASICs targeting a traditional rad-hard foundry, which may be more than two generations behind commercial foundries, applying hardness-by-design methodology at a commercial foundry, and directly targeting a commercial foundry using commercial design practices.

An improved charge separation technique for metal–oxide–silicon (MOS) capacitors is presented which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. Using high-frequency capacitance–voltage measurements, radiation-induced inversion voltage shifts are separated into components due to oxide trapped charge, interface traps, and deactivated dopants, where the latter is computed from a reduction in Si capacitance. In the limit of no radiation-induced dopant deactivation, this approach reduces to the standard midgap charge separation technique used widely for the analysis of room-temperature irradiations. The technique is demonstrated on a p-type MOS capacitor irradiated with Co60 γ rays at 100 °C and zero bias, where the dopant deactivation is significant.

Metal-oxide-silicon capacitors fabricated in a bi-polar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100 C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H{sup +} ions in the oxide and Si layers and the availability of holes in the Si depletion region. Capacitor data from unbiased irradiations were used to simulate the impact of acceptor neutralization on the current gain of an npn bipolar transistor. Neutralized acceptors near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may enhance radiation-induced degradation of linear circuits at elevated temperatures.

Metal-oxide-silicon capacitors fabricated in a bipolar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100/spl deg/C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H/sup +/ ions in the oxide and Si layers and the availability of holes in the Si depletion region. The capacitor data were used to simulate the impact of acceptor neutralization on the current gain of an irradiated npn bipolar transistor. Neutralized accepters near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may complicate hardness assurance test methods for linear circuits, which are based on elevated temperature irradiations.

Neutron and proton irradiations have been used to improve the latchup susceptibility of CMOS test structures fabricated at a radiation-tolerant commercial submicron CMOS foundry. The test structures were varied in critical spacing dimensions to represent a range of layout conditions in typical CMOS circuits. SPICE simulations were used to relate changes in latchup tolerance to reduced parasitic bipolar gains and increased well and substrate resistances in these CMOS circuits. It is shown that decreasing transistor gains and increasing resistances can have competing influences on latchup threshold. These competing effects can explain the observed initial reduction in latchup threshold for some proton irradiation conditions

MOSFETs fabricated in the commercial Chartered Semiconductor 0.35-μm CMOS process were characterized with respect to the effects of total dose irradiation. Gate oxide threshold voltage shifts at 100 krad(Si) for both minimum geometry 0.70/0.35 NMOS and PMOS transistors biased for worst-case shifts were less than 20 mV. Off-state field leakage currents for isolated NMOS transistors were below 10 nA at 100 krad(Si), but became large at 300 krad(Si). The effect of a post-irradiation high temperature anneal was to lower these leakage currents to less than 100 pA. PMOS transistors exhibited less than 10 pA leakage for doses up to 300 krad(Si). Measurements on edgeless annular NMOS transistors showed no significant increase in leakage current with total dose, indicating that the increased leakage observed in standard NMOS transistors is the result of field leakage associated with inversion in the bird's beak region at the transistor/field oxide interface. C-V measurements on field-oxide capacitors over substrate biased for worst-case threshold voltage shifts showed the capacitors did not invert at 100 krad(Si) for 3.3 V operation. Measurements on ring-oscillators biased dynamically during irradiation showed no significant change in the gate delay or power up to 300 krad(Si) total dose, suggesting that for actual digital circuits applications, functionality and performance may be able to be maintained to doses substantially above 100 krad(Si)

Oxide trapped charge, field effects from emitter metallization, and high level injection phenomena moderate enhanced gain degradation of lateral pnp transistors at low dose rates. Hardness assurance tests at elevated irradiation temperatures require larger design margins for low power measurement biases.

Microelectromechanical Systems (MEMS) are micron-to-millimeter size electromechanical devices that are fabricated using modified semiconductor batch-fabrication techniques. We believe that MEMS technology will have a significant impact on future space systems by 1) reducing the size, mass, power, and cost of individual sensors and actuators used throughout spacecraft and launch vehicles and 2) ultimately reducing overall spacecraft size. At the Aerospace Corporation, we are focusing on near and far-term applications of MEMS in space systems for reduced mass, improved performance, higher reliability, increased health and status awareness, and reduced life cycle costs. Specific tasks include the development of micro-propulsion technology for microsatellites (1-to-100 kg mass) and nanosatellites (1-to1000 gram mass), the development of a flight-qualifiable GN&C (guidance, navigation, and control) unit using a GPS receiver and MEMS inertial sensors, and the development of a MEMS-based wireless multiparameter sensor.

Enhanced low-dose-rate gain degradation of ADI RF25 lateral pnp transistors is examined as a function of the bias at which the gain is measured. Degradation enhancement at low dose rates diminishes rapidly with increasing measurement bias between the emitter and the base. Device simulations reveal that interface trap charging, field effects from oxide trapped charge and emitter metallization, base series resistance and high-level carrier injection all contribute to this behavior. As a practical consequence, accelerated hardness assurance tests of this device require higher irradiation temperatures or larger design margins for low power applications.

Enhanced low-dose-rate gain degradation of AD1 RF25 lateral pnp transistors is examined as a function of the bias at which the gain is measured. Degradation enhancement at low dose rates diminishes rapidly with increasing measurement bias between the emitter and the base. Device simulations reveal that interface trap charging, field effects from oxide trapped charge and emitter metallization, base series resistance and high-level carrier injection all contribute to this behavior. As a practical consequence, accelerated hardness assurance tests of this device require higher irradiation temperatures or larger design margins for low power applications.