This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance of SFVBP could remain a bottleneck. Direct Backside Contact (DBC) based schemes offer best cell level scaling. A novel self-aligned backside contact (SABC) scheme integrated with nanosheet transistors is demonstrated with immunity to misalignments in backside contact formation. The structure exhibits good device characteristics and satisfactory reliability.

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.

Early in a semiconductor node’s process development cycle, the technology definition is locked down using somewhat risky assumptions on what the process can deliver once it matures. In this early phase of the development cycle, detailed design rules start to be codified while the wafer patterning process is still being fine-tuned. As the process moves along the development cycle, and wafer processes are dialed-in, key yield improvement efforts focus on variability reduction. Design retargeting definitions are tweaked and finalized, and the use of finely tuned etch models to compensate for process bias are applied to accurately capture the more mature wafer process. The resulting mature patterning process is quite different from the one developed during the early stages of the technology definition. In this paper we describe an approach and flow to drive continuous improvement in the mask solution (OPC and MBSRAF) later in the process development and production readiness cycle stage. First, we establish the process window entitlement within the design-space by utilizing advanced mask optimization (MO) combined with the baseline process (i.e., model, etch compensation, and design retargeting). Second, gaps to the entitlement are used to identify and target issues with the existing OPC recipe and to drive continuous improvements to close these performance gaps across the critical design rules. We demonstrate this flow on a 20 nm contact layer.

We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more predictive than compact model but much faster then the physics-based MC model. However simplifying the model might lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm based lithography process using DSA.