Purpose This study aims to investigate the fracture behavior and reliability of large-area sintered Cu for power electronic packaging, with a specific focus on the influence of the "edge effect" on interfacial performance and structural deformation.Design/methodology/approach By fabricating sintered Cu joints with different dimensions (8 & times; 8 mm2, 16 & times; 16 mm2 and 32 & times; 32 mm2) and evaluating their microstructures, mechanical properties and warpage behavior, the mechanism of nonuniform performance degradation induced by the "edge effect" is revealed.Findings As bonding area increases from 8 & times; 8 mm2 to 32 & times; 32 mm2, shear strength drops from 105.18 MPa to 61.36 MPa, while edge porosity rises from 13.92% to 28.87%. High-temperature storage and thermal cycling (TC) exacerbate void expansion, with edge porosity reaching 37.73% after TC. Simulation reveals that stress induced by coefficient of thermal expansion mismatch increases nonlinearly with area, correlating with strength degradation zones. Experimental warpage matches simulation results within 6% error.Originality/value This study provides a crucial experimental basis and theoretical support for the process optimization and reliability design of large-area sintered Cu.

High-bandwidth memory (HBM) faces critical power integrity challenges in high-stack configurations due to elongated power delivery paths and increased parasitic inductance. This paper proposes a dual-interposer HBM architecture with an interposer–HBM stack–interposer configuration, integrating an additional top interposer embedded with chip capacitors. This topology redesigns the HBM’s power distribution network, reducing PDN impedance, and this technology enables bidirectional vertical power supply to DRAM chips during moments when they require current. The PDN impedance is systematically compared with a conventional trench-capacitance-enhanced structure (Structure A) and a deep-trench-capacitance-enhanced structure (Structure B). Results show that at 0.1–11.2 GHz, the proposed structure reduces peak PDN impedance by 66.41% and 65.7% versus Structures A and B, respectively, and decreases the loop inductance of the top-layer DRAM chip by 66.71%. The top interposer’s redistribution layer forms a parallel-plate capacitor complementing the embedded chip capacitors, achieving wideband impedance suppression. Without modifying existing protocols, this architecture provides a system-level PDN optimization strategy for high-stack HBM, offering quantitative insights for capacitor selection and layout design.

Through the combination of terahertz spectroscopy and theoretical calculations, a comprehensive analysis has been conducted on the molecular vibrational characteristics and intermolecular weak interactions of methylparaben at varying temperatures.

The curing behavior of underfill adhesive is one of the key factors determining the reliability of micro-interconnections in flip-chip packaging. This study aims to systematically elucidate the structure-property relationship of epoxy-based underfill adhesive, spanning from chemical curing to macroscopic shear strength. By integrating non-isothermal and isothermal differential scanning calorimetry with in-situ attenuated total reflection–Fourier transform infrared (ATR–FTIR) spectroscopy, the characterization accuracy of various curing kinetic models for the curing behavior of the underfill adhesive was comparatively evaluated. The findings reveal that the n-th order curing kinetics model leads to significant fitting distortion due to its neglect of the inherent autocatalytic effect within the system. In contrast, the Sesták–Berggren and Kamal–Sourour models, which incorporate autocatalytic mechanisms, achieve substantial optimization in characterization performance. The model-free isoconversional method quantitatively reveals the competition mechanism between hydroxyl-induced autocatalysis and gelation-triggered diffusion-controlled stages, confirming the physical essence of the dynamic evolution of activation energy with the degree of curing. Furthermore, in-situ ATR–FTIR spectroscopic data provide robust evidence for the intrinsic consistency between macroscopic heat flow and microscopic functional group transformation. Crucially, the shear strength of the micro-interconnection joints exhibits an exponential non-linear growth with the degree of curing. Notably, during the cross-linking densification stage after the degree of curing transcends 0.95, the shear strength undergoes a significant leap of 48.39

High-frequency transmission loss in Redistribution Layer-Through Silicon Via (RDL-TSV) interconnect structures is a critical factor influencing the performance of three-dimensional integrated circuits. This study aims to enhance the prediction accuracy of high-frequency losses by balancing the training accuracy and computational efficiency of traditional full-wave simulation and equivalent circuit models. A Physical Information Convolutional Neural Network (PI-CNN) prediction model was developed based on convolutional neural networks, incorporating the skin effect as physical guidance. A multi-criteria decision-making framework was then proposed by integrating the PI-CNN model with a genetic algorithm. Results show that the PI-CNN model achieves stable single-prediction times under 3 s, with prediction loss errors below 0.1 dB and an R2 value of 0.987, significantly improving the accuracy of high-frequency loss prediction. Through multi-criteria decision optimization, the randomness inherent in genetic algorithms enables systematic exploration of favorable design options within the design space. This approach ensures that the final design maintains consistent performance and robustness under anticipated manufacturing variations. The study provides a data-driven, physics-guided approach for evaluating and optimizing high-frequency performance in advanced packaging.

The accuracy of viscoelastic testing and fitting will directly affect the stress and warpage prediction ability of advanced microelectronic packaging. It is necessary to directly verify and improve the accuracy of the viscoelastic model and the temperature shift factors. This study proposes and validates an improved fitting method for the viscoelastic generalized Maxwell model, guided by stress relaxation curves. The proposed method aims to reduce a priori empirical errors associated with determining temperature shift factors based on the time–temperature superposition principle and to overcome limitations in the fitting accuracy and applicable range of the Williams–Landel–Ferry (WLF) equation. Using experimentally measured stress relaxation curves as benchmarks, improved temperature shift factors are calculated via a characteristic node approach, enabling the construction of an enhanced master curve and refined fitting parameters for the viscoelastic constitutive model. An interpolation method is additionally employed to replace WLF equation fitting for calculating temperature-dependent parameters via shift factors. To validate the accuracy of the proposed method, four finite element methods for viscoelastic parameters were analyzed, and the polyimide stress relaxation process was simulated using the finite element method and compared with experimental results. The findings demonstrate that, compared with traditional fitting approaches, the proposed method significantly improves the accuracy of viscoelastic parameters and enables reliable prediction of stress relaxation behavior across a range of temperatures. It provides an engineering approach for high-precision material testing for semiconductor industry research and development.

Electrically conductive adhesives (ECAs) play a vital role in the field of electronic packaging, favored for their high bonding strength, rich formulation design, good heat resistance and low curing shrinkage. The reliability of ECA interconnections in the process of temperature fluctuation will directly affect the performance and service life of electronic components. In order to study the reliability of ECA interconnections under the temperature cycling test, the silicon chip was directly bonded to the FR-4 substrate by an ECA. The temperature range was -40 degrees C to 85 degrees C, with a total of 1000 cycles. The material properties of the ECA were characterized by dynamic mechanical analyzer (DMA) and thermomechanical analyzer (TMA). Furthermore, finite element simulations leveraging the method of element birth and death were conducted to assess the effects of crack or delamination of the ECA. The findings reveal that temperature cycling induce disparate thermal strains within the composite structure stemming from the differing coefficients of thermal expansion (CTE) among the materials involved. This resulted in the warpage of the silicon chip. After enduring 1000 cycles of temperature changes, the warpage exhibited a decreasing trend. And delamination at the interface between the ECA and the substrate was also observed. Besides, the simulation found that the stress response of the ECA was particularly telling, peaking at -40 degrees C and demonstrating a swift decline in stress at high temperatures. What's more, a distinct pattern emerged regarding stress and warpage, with maximum values concentrated at the outermost corner. Therefore, during the temperature cycle, the outermost corner of the interface between the ECA and the substrate is more prone to failure. This provides the reference of experimental results and the prediction of finite element simulation method for packaging process and reliability testing.

As power electronic devices advance towards higher power density and integration, the packaging interconnects face increasing reliability and performance challenges under high-temperature and high-power conditions. Silver sintering technology, known for its low sintering temperature, hightemperature stability, and excellent electrical, thermal, and mechanical properties, is recognized as a critical enabler for the packaging of next-generation high-temperature power devices. However, this technology faces significant process challenges: traditional pressure-assisted sintering applies excessive mechanical stress, potentially damaging the chip structure, while pressureless sintering lacks sufficient external driving force to achieve the desired densification, limiting its use in high-reliability packaging.This study introduces an innovative non-contact, microfine gas flow-assisted pressure sintering method that allows for precise pressure control. Key process parameters, such as sintering temperature, pressure, and gas flow rate, were systematically investigated to examine their effects on the densification behavior and microstructural evolution of silver sintering. Parallel experiments comparing pressureassisted and pressureless sintering were conducted to evaluate the porosity, microstructure, and mechanical properties of the sintered interconnects under different conditions. The results demonstrate that this method provides a uniform, controllable pressure distribution on the chip surface, with a pressure uniformity coefficient exceeding 80%, significantly reducing the risk of mechanical damage due to localized stress concentrations. Additionally, it delivers a significant intrinsic driving force for the densification of silver sintering, enhancing material diffusion and migration during the process. This results in reduced porosity, approaching the densification levels of traditional pressure-assisted sintering. Ultimately, the sintered interconnects exhibit high density, excellent mechanical strength, and superior thermal-electrical performance, offering a robust process solution for highperformance, high-reliability power electronic packaging.

High-density interconnect printed circuit boards (HDI-PCBs) have been widely used in complex electronic products from mobile phones to computers. Warpage is a key issue affecting their reliability and performance. In this study, the multi-layer HDI-PCBs with different copper residual ratios (CRR) was modeled based on the trace mapping method. The two-material equivalent model was used to equivalently model the copper trace layer. The effect of curing shrinkage was simulated by the method of equivalent coefficient of thermal expansion (CTE). Finite element analysis (FEA) systematically investigated the impacts of CRR variations, copper layer modeling strategies, and adhesive curing on chip warpage. The study indicates that variations in the CRR exhibit specific trends in influencing chip warpage, with a 90% CRR configuration demonstrating a nearly centrosymmetric warpage distribution. Compared to the trace mapping method, the two-material equivalent model achieves consistency in warpage trends while reducing computational time, despite minor deviations in accuracy. Curing shrinkage plays a critical role in modulating post-curing warpage, and precise characterization of adhesive properties during the early curing stage (e.g., elastic modulus, CTE, and curing shrinkage rate) will enhance prediction accuracy. These insights establish a computationally efficient multi-scale modeling paradigm for warpage prediction in advanced packaging, providing guidelines for material selection and process optimization in high-density interconnects.

Digital Twin (DT) technology epitomizes a cutting-edge advancement in the domains of simulation and modeling, assuming a pivotal role within high-fidelity physical models by meticulously emulating the dynamic behaviors of physical systems. This proficiency furnishes a robust underpinning for predictive analytics, optimized design paradigms, and control methodologies. Nonetheless, conventional high-fidelity physical models confront substantial constraints in intricate systems, particularly amid multi-physics coupling analyses, wherein computational intricacy surges exponentially, necessitating prodigious resources and temporal investments. In response to these exigencies, data-driven digital twin models have proliferated, leveraging surrogate models and machine learning algorithms to extrapolate system representations directly from disparate historical datasets. These paradigms endeavor to delineate performance degradation trajectories and prognosticate prospective failure loci. Notwithstanding these merits, their prognostic fidelity and robustness remain susceptible to degradation under regimes of scant data volume, suboptimal data integrity, or pronounced system nonlinearity. To surmount these impediments, the present investigation proffers a hybrid digital twin paradigm predicated on Backpropagation Neural Networks (BPNN), meticulously engineered for multi-physics field analyses in System-in-Package (SiP) encapsulation. This methodology refines the chip-adhesive-thermal interface material-electromagnetic compatibility (EMC) architecture through the appraisal of an expansive array of design parameters, encompassing material attributes (e.g., thermal conductivity, elastic modulus) and geometric attributes (e.g., dimensions, layer thicknesses). By amalgamating the exactitude of high-fidelity physical models with the computational expedience of data-driven methodologies, this hybrid construct facilitates expeditious and real-time prognostication and amelioration of thermomechanical stresses in encapsulated apparatuses, thereby augmenting device dependability and efficacy. For emergent SiP encapsulations, the approach entails the allocation and synthesis of material properties, the derivation of superlative design parameter configurations via the machine learning apparatus, and the corroboration of resultant outcomes through high-fidelity physical simulations. Moreover, the framework elucidates the ramifications of diverse encapsulation process parameters on thermomechanical efficacy, proffering data-driven directives and theoretical perspicacity for prospective SiP delineations. This endeavor appreciably contributes to the evolution of efficacious and dependable encapsulation technologies.

With the increasing demands of high-performance electronic devices on the dimensional stability and reliability of large-area package substrates, conventional organic substrates are prone to warpage and solder joint failure under thermo-mechanical loading, which has become a critical bottleneck for advanced packaging technologies. To address this issue, this study proposes a structural design strategy that locally embeds a glass core within large-area package substrates to enhance their thermo-mechanical performance and improve solder joint reliability. A three-dimensional finite element model was established, incorporating the chip, microbumps, underfill, glass core, and organic substrate, with the viscoplastic constitutive behavior of the solder included to characterize its time-dependent mechanical response under temperature cycling from $-55^{\circ} \mathrm{C}$ to $125^{\circ} \mathrm{C}$. The substrate warpage and solder joint stress-strain distributions were systematically evaluated, and the Engelmaier-modified Coffin-Manson model was employed to predict the thermal fatigue life of the solder joints. The results indicate that the local glass core significantly reduces substrate warpage, with maximum deformation much smaller than that of conventional fully organic substrates. Meanwhile, the stress and strain distributions of the solder joints become more uniform, effectively mitigating high stress concentrations in critical regions, thereby substantially extending the predicted solder joint lifetime, particularly in high-risk areas such as package corners. Overall, the study demonstrates that local glass core embedding effectively suppresses substrate warpage and enhances solder joint durability, providing a feasible strategy and engineering reference for the structural optimization and reliability design of large-area highperformance package substrates.

With the continuous advancement of microelectronics technology towards higher frequencies and speeds, System-in-Package (SiP) has become one of the core packaging technologies for many product applications. As chip clock frequencies continue to rise, the entire system becomes more sensitive to signal integrity issues. How to mitigate signal integrity problems in high-speed interconnects within packages has become a critical challenge. To investigate far-end crosstalk (FEXT) and impedance discontinuity issues in high-frequency signals within packages, we implemented tabbed routing structures to optimize transmission links. The study examined the effects of Ltab, Stab, Wtab, and the number of tabs on FEXT and impedance characteristics. Using single-factor analysis and orthogonal experimental design combined with range analysis, we conducted simulation studies to evaluate each factor's influence, ultimately obtaining two optimal parameter combinations that meet design requirements. The results revealed that Wtab and the number of tabs have more significant impacts on both FEXT and impedance. Eye diagram analysis provided visual comparison of the two optimized combinations, demonstrating that the configuration with impedance closest to 50 ohms achieved maximum improvement-increasing eye height from 0.445V to 0.452V and eye width from 79.58ps to 81.25ps. Furthermore, when FEXT parameters already met requirements, additional optimization of impedance parameters to enhance continuity yielded better performance improvements for high-speed signal transmission.

Driven by the increasing demand for high power density in power electronic devices, copper sintering technology has emerged as a critical process in advanced packaging and interconnection due to its inherently superior thermodynamic properties. However, the absence of active flux in the solder may lead to insufficient lubrication between the chip backside and the base, or issues such as high-temperature plastic deformation of the solder and inadequate wetting of the chip surface. These factors result in the formation of a certain volume fraction of randomly distributed voids within the solder layer of the chip. Such defects impede heat dissipation, thereby increasing thermal resistance. This study investigates the mechanical influence mechanism of voids defects in the solder layer of power electronic modules and systematically analyzes the effect of voids defects in the nano-copper sintered layer on thermal stress distribution and structural reliability. By designing and regulating voids models with varying types and sizes through controlled variables such as voids radius and spatial position, the research reveals that the presence of voids significantly elevates the maximum junction temperature of the chip and induces localized thermal stress in the solder layer. Additionally, as the hole radius increases, the overall temperature of the module rises, and the maximum equivalent stress of the solder layer increases. When the hole rate exceeds 20%, the upward trend of the maximum equivalent stress of the chip increases, accelerating the failure time of the power module. This discovery provides a key theoretical basis for the reliability design of power modules.

With the rapid development of 5G communication and millimeter-wave (mm Wave) technology, the severe challenges posed by high path loss and transmission attenuation of high-frequency signals have become critical constraints for 5G mm Wave applications. Fan-out wafer-level packaging (FOWLP), with its compact size, high I/O density, and low-loss characteristics, is recognized as an excellent solution for Antenna-in-Package (AiP) implementation. This study focuses on the warpage behavior of epoxy molding compound (EMC) during the post-curing process in antenna packaging. A combined approach of experimental measurements and finite element analysis (FEA) is employed to systematically investigate the influence of various structural parameters on the warpage performance of the package. The results demonstrate that the viscoelastic properties of EMC play a critical role in warpage behavior during the post-curing process. Compared with the linear elastic model, the viscoelastic model more accurately captures the stress relaxation behavior of the material, effectively reducing residual stress and overall warpage. Moreover, the viscoelastic model better reveals the coupling relationship between structural design parameters— such as carrier thickness, chip thickness, and layout—and the thermo-mechanical response, offering valuable insights for material selection and structural optimization in engineering applications.

With the widespread adoption of wearable smart health monitoring devices, the performance of their core component that the PPG sensor has become increasingly critical. Traditional PPG sensors face limitations such as bulky size, high power consumption, and slow response in their LED light sources, significantly constraining device battery life and measurement accuracy. To address these limitations, this study proposes replacing traditional LED chips with Micro-LED chips based on third-generation semiconductor technology as the light source for PPG sensors. Single-channel PPG sensor models were constructed using both traditional LED chips and Micro-LED arrays. Based on the Beer-Lambert law and the Henyey-Greenstein function, a multi-layer skin tissue model was developed in TracePro. Monte Carlo-based ray tracing simulations were employed to evaluate key performance metrics, including radiant flux on the detector and illumination uniformity. Comparative analysis revealed that the PPG sensor utilizing Micro-LED arrays outperformed its traditional LED counterpart under identical drive currents. Specifically, it demonstrated higher irradiance and superior illumination uniformity, with detector light intensity distribution uniformity improving by 5 similar to 6%. These findings validate the performance advantages of Micro-LED technology in enhancing PPG sensors, providing valuable insights for developing next-generation miniaturized, low-power blood oxygen monitoring sensing devices.

The Sn58Bi solder alloy is widely used in microelectronics as a low-temperature soldering alloy, with creep being its notable deformation mode. To effectively characterize the creep behavior of this alloy, a uniaxial-tensile-creep test was designed herein. The creep deformation mechanism was analyzed by comparing the microstructure of the alloy before and after the test. The relevant creep material constants were obtained by fitting the experimental data with the Norton power-law and Kachanov–Rabotnov (K–R) creep models, which were then used to theoretically predict creep strain. In addition, the two models were implemented in finite-element simulations through custom material constitutive equations. Results suggest that only the second and third creep stages are notable. During creep, the numbers of subgrain boundaries and low-angle grain boundaries as well as the nucleation rate of recrystallized grains considerably increase, inducing grain refinement. The predictions of the K–R model are more consistent with the creep test results than those of the Norton model, and the minimum fitting accuracy of the K–R model is 0.865. The K–R model is considerably more suitable here while Norton model could not describe the third creep stage. The simulated and theoretical results are consistent, indicating that the employed simulation method effectively describes the creep characteristics of the Sn58Bi solder alloy. Overall, the proposed method and constitutive model parameters are effective for analyzing the creep and reliability of Sn-based alloys employed in microelectronics.

This study aligns with the development trend of glass substrate packaging. The research aims to analyze the delamination of the substrate–adhesive layer-chip trilayer structure in packaging through experimental testing to obtain interface strength parameters. Subsequently, an iterative process combining experiments and simulations was applied to establish a cohesive zone model characterizing crack initiation and propagation. Finally, reliability analysis of the packaging structure was conducted. The results indicate that the load–displacement curves during sample loading can be experimentally acquired, enabling the determination of critical load values triggering interface delamination. The specific locations of delamination within the packaging structure are also clearly observed. Through simulation fitting, cohesive parameters reflecting interface strength are obtained, which serve as the basis for evaluating interface delamination fractures. Furthermore, applying the calibrated cohesive parameters to the established glass substrate model, simulation analysis evaluates delamination risks under thermal conditions.

This paper conducts thermal analysis and optimization for a specific high-power-density System-in-Package. By employing finite element analysis software ANSYS Icepak, the structure and parameters of the substrate were optimized to reduce the chip junction temperature of the System-in-Package, thereby enhancing the heat dissipation efficiency of the device. Firstly, single-factor analysis was conducted on the substrate structure and parameters affecting the heat dissipation of the packaging, including the number of vias, via plating thickness, copper layer thickness, copper coverage, substrate thickness, and BT material, to evaluate the influence of each factor on chip junction temperature and packaging thermal resistance. Next, the significance of the six parameters on chip junction temperature was analyzed through orthogonal experimental analysis. Finally, response surface analysis was conducted on the significant continuous variables to determine the optimal combination of substrate structure and parameters after optimization. The optimized chip junction temperature was 101.798 degrees C, and the packaging thermal resistance was 27.43 C/W. Compared with before optimization, the chip junction temperature decreased by 15.23% and the packaging thermal resistance decreased by 19.23%

In recent years, underfill technology has been playing an increasingly important role in advanced packaging, and the associated reliability issues of bonding structures have become more significant. Particularly, the well-formed bonding interface formed by the underfill adhesive in the packaging structure determines the ability to resist cracking and delamination, which is crucial for ensuring the reliability of electronic packaging devices. Currently, most research has focused on various bonding interfaces of underfill in FC packaging. However, with the rapid development and application of advanced packaging technologies such as 2.5D and 3D, the failure issues exposed by underfill in their structures have become more prominent. In this study, a commercial underfill material was used to prepare a simplified Si/underfill/substrate bonding structure, designed to mimic the widely adopted structure of silicon interposer/underfill adhesive/substrate in actual 3D packaging. A combined experimental and finite element modeling method was proposed to determine the bonding strength of the Si/underfill/substrate structure. This method conducts interface analysis based on the theory of fracture mechanics, conducts single cantilever beam test and lap shear test on the two main failure modes of model I and model II, and then uses the test results as simulation parameters. Through iterative simulation, a cohesive zone model (CZM) characterizing crack initiation and propagation was established. In summary, the method of establishing the CZM model can not only evaluate the delamination risk of the Si/underfill/substrate interface in 3D packaging but also provide a convenient and cost-effective approach for analyzing other similar interface delamination issues.

At present, fan-out packaging has become the mainstream chip packaging technology and is considered one of the latest and most promising technologies. However, after the filler is filled and cured into the mold, the problem of chip warpage due to stress is unavoidable. Therefore, accurately predicting the viscoelastic behavior of the underfill during the curing process can help predict warpage and reasonably improve the packaging structure to reduce the warpage effect. In this paper, the influence of the curing degree of the bottom filling layer on the warpage of the chip during the curing process of liquid bottom filling was investigated. The study began with the experimental characterization of temperature-dependent material properties of the underfill system, through dynamic mechanical analysis (DMA) and thermodynamic analysis. In addition, the heat of reaction and degree of cure during curing are measured by differential scanning calorimetry (DSC) testing. In order to save computing power, reduce the difficulty of simulation calculation, and the model has a high degree of symmetry, 1/4 of the simulation model was taken for research. The model consists of a substrate, a bottom filling, a microbump, an RDL layer, a chip and an EMC layer. Due to the focus on the viscoelastic mechanical behavior of the bottom filler, the RDL layer is simplified to two layers of PI polyamide sandwiched between a copper layer. The temperature load given to the entire model was 25 degrees C to 110 degrees C for 20 minutes, then back to room temperature. The simulation results show that significant changes in warpage occur after the underfill reaches 90% cure degree. Specifically, starting from the cooling stage, the warpage decreases substantially and reaches zero at a certain temperature point. Finally, reverse warpage forms at room temperature, changing from a "smile" to a "frown.".