This paper presents a method for characterizing molding compounds dedicated to integrated circuit packaging. The method is based on the use of a three-conductor transmission line known as a “trident waveguide”. The objective is to jointly extract the relative complex permittivity ($\varepsilon_{r}$) and permeability ($\mu_{r}$) of a resin sample over the $300 \text{kHz}-9 \text{GHz}$ frequency band. The sample is traversed at its center by the three conductors, which pass through holes previously drilled in the resin with a diameter matching that of the conductors. This configuration provides a practical solution given the low technological maturity of these resins: the manufacturing process enabling the integration of metallizations (transmission lines, etc.) is still under development. The configuration was also selected for two reasons. First, it offers strong conductor/material interaction due to its distributed nature. Second, the resin cross-section is homogeneous along the propagation direction of the signals, which simplifies the extraction of $\varepsilon_{r}$ and $\mu_{r}$. The work presented notably includes a validation of the characterization method through simulation. A measurement-simulation comparison is also performed to validate the operation of the test vehicle integrating the resin.

Insulating materials used for the packaging of integrated circuits play an important role in the electrical performance of the new System-in-Package (SiP), designed to support flows greater than 10 Gbits/s. These insulating materials must have a low relative permittivity and low dielectric losses up to several tens of GHz in order to insure the integrity of the propagated signals. In this paper the in-situ characterization of molding resins and core materials, used respectively for the encapsulation and the package substrate of chips of new 3D SiP on Board (SiPoB 3D), is carried out up to 100 GHz. These characterizations are performed after the manufacturing process (deposition, drying) of insulators and in their final conditions of use (thicknesses of a few microns, thinning, polishing) since their permittivity is highly dependent on the entire process. The characterization methodology is based on two original techniques: the analysis of the signal propagation on specially optimized CPW lines (coplanar lines) and the analysis of the reflection coefficient measured at the end of a CPW RF probe directly set down the surface of the insulator sample. This new technique makes it possible to overcome whole metallization steps required to achieve waveguide structures used in most material characterization techniques. In addition, the complex permittivity can be 2D-scanned on the entire surface area of the sample of material under test with our technique.

A wide band (1 GHz-67 GHz) characterization method of insulator layers is presented. This method is well suitable for a fast, simple and accurate extraction of permittivity of insulators used in interconnects networks. Concerning losses, reto-simulations must be achieved to extract the loss tangent, due to the fact that the extraction of G/(C.ω) includes extrinsic effects. So both lossless and loss cases will be discussed. This non-destructive method and low-cost method presents strong advantages because no specific device under test, no metallic deposit and no etching are required. Measurements are performed using a coplanar GSG RF microprobe directly set down on the dielectric material to characterize.

Electrical Co-design of IC-package-PCB products for Set-Top Box applications has been changing quickly in the past years. The new generation of processors (A53, A57 ... ) is indeed bringing interesting challenges as the business seems to be looking for the most power efficient CPU architectures (DMIPS/W). Moreover standards of high-speed interfaces are being released with increasing speeds (HDMI2.1, USB3.1, LP/DDR4 ... ). This paper presents the achievements and the challenges in the field of IC-package-PCB electrical simulation and co-design, based on examples of recent product developments. Correlations between simulations and measurements are presented as it plays an important role in the development of the simulation methodologies. The main focus of this paper is on power analysis, power integrity (PI) studies and performance prediction. Then a case of signal integrity (SI) studies is briefly discussed. Conclusions on links between physical IC-package-PCB co-design and EM/PI/SI are presented.

This paper has shown interesting decoupling solutions of PDNs, when they should be employed and what tradeoff between electrical performance and cost should be considered. It has shown through a concrete example the PDN decoupling strategy done on a typical set top box product and its validation through measurement and simulation. Finally it has briefly discussed the correlation capability of modelling versus measurement.

Ball Grid Array packaging for integrated circuits permits to address most standard electronics applications with recognized and proven advantages of low cost, high volume capability, design flexibility & electrical/thermal/mechanical performances. However, standard BGA package technology approach, i.e. cost driven technology selection in other words, is reaching some limits for latest and future high speed and RF applications. In addition to the evolution of package design rules (enabling higher density and integration capabilities) and the evolution of assembly processes (such as the transition from die wire bonding to flip chip connection), some other issues must be considered to address these applications running at very high data rates and / or high working frequencies. Amongst these considerations, the key points to target package performances fitting with the product specifications are linked to the technology choices, especially for the materials of the laminate substrate of the package. For standard BGA materials there is currently a lack of electrical properties data at very high frequencies that may be problematic to determine package electrical behavior. In addition, current tolerances of substrate manufacturing may impact drastically overall performances whereas they were not so harmful for previous product generations running at slower frequencies. Impact of the material electrical properties and manufacturing tolerances will be demonstrated thru concrete examples and simulation results. The actions to lead with substrate manufacturers and material providers to manage successfully these high speed and RF signals constraints faced by the BGA IC packaging and to anticipate the coming ones will also be discussed.

Almost every electronic device is sensitive to electrostatic discharges. The charged device model (CDM) is today used by the industry to characterize the electrostatic discharge events that occurs in an automated industrial environment. Based on this model, the JEDEC and ESDA give some standards that, with specific test equipment, rank the electronic device by their ability to withstand different level of electrostatic discharges. To ensure the compatibility of its products with those standards, the company designs some dedicated protections at the silicon level. The counterpart of those protections is that they take additional area on the silicon. Therefore a particular attention is given to fit the standard constraints without oversizing the protections. In ESDA and JEDEC standards, the rating is directly determined by the voltage level applied between positive and negative electrodes of the tester. If this voltage level contributes to the amplitude of current peak that will happen during the discharge, it is also highly dependent on the package under test, whose dimensions are a major contributor to the resulting current peak for a known voltage. This article shows first, the limitation of the JEDEC and ESDA standards approach on today BGA packages. Secondly, it presents a simple way to determine the capacitance between the package and the tester, thus predicting the shape of the electrostatic discharge crossing the product. Among the different BGA packages developed in the company, it also shows which packages are reaching the standard limits.

The scope of this article is concerning the electrical modeling tools used for the package parasitic extraction. Many 3D electrical modeling tools are on the market today enabling different type of electrical models to represent the electrical behavior of the packages. Semi-conductor companies are using many of them to address a wide range of applications, going from Communications, Consumer and Computer to Automotive and Industrial market segments. To get the right performances at the rights cost for all of these applications, the diversity of developed packages is considerable requesting also several strategies for the electrical modeling. In parallel, IC interfaces speed is increasing for many of these applications fields and the new SOCs (System on Chip) are including more and more interfaces like USB, SATA etc…This is leading to an increasing impact of the package in term of electrical behavior. This trend makes electrical models mandatory for packages in a growing part of the product designs. This paper will present several types of packages to be modeled to cover the different products. The usage and limitations of several modeling tools in regards with the applications will also be presented. Some additional limitations will appear for advanced packaging required by the most challenging products. Finally, the direction chosen to overcome these challenges through increasing collaborative work with CAD vendors and Institutions will be presented.