This paper describes the operation of a proposed method of access to bidirectional local area network buses-called timed packet release or TPR. The method is based on a system of time delays in the nodes, reckoned from a timing reference signal and provides collision free deterministic access for queued packets. A comparative evaluation of the performance of TPR with other methods of bidirectional bus access such as token passing and the reservation protocols is provided. Results, obtained using discrete event simulation models, are presented for the various access protocols. Performance is measured in terms of the average delay-throughput characteristics of the networks. The implementation aspects of TPR are reviewed briefly.

Efficient transfer of information between all levels of a manufacturing organisation is becoming an increasingly essential element in maintaining industrial competitiveness. Since manufacturing is a distributed activity with varying levels of time-criticality at different levels in the hierarchy, the architecture of the computer communication networks must match these fundamental requirements. One appropriate solution is the General Motor's Manufacturing Automation Protocol local area network-MAP. Another possibility, proposed in this paper, is to use Ethernet for higher level communications, where time is less critical, and to supplement this with a "real-time Ethernet" at the lower levels. This paper therefore describes a system designed to convert segments of a factory wide Ethernet network to support hard real-time operation. The system, called TEMPRA, uses a simple method to control the release of Ethernet packets in a collision free manner. High priority real-time operation is guaranteed to the user through a dual stack architecture, which has a separate deterministic stack for high reliability real-time messages-whilst background traffic is handled using CSMA/CD and TCP/IP protocols.

Emerging versions of distributed real-time systems employ sensor fusion and distributed intelligent knowledge bases and thus require repid interchange of data between processors and subsystems. Physically distributed systems are usually interconnected by one of the established local area network architectures. Established LAN standards address, primarily, the needs of non-real-time data traffic. A new LAN architecture, Instanet, which incorporates a logically separate channel to arbitrate on the access rights of different priorities of traffic has been developed to support the needs of distributed real-time systems. This paper gives an overview of the Instanet architecture and presents analytical and simulation results of its performance under different traffic loadings.

Local area network technology has to date generally focused on the problems of interconnecting high speed computing devices. Thus, where the connection of (primarily) low speed devices to a network is required, this has to be achieved by means of a star wired concentrator.

The real-time facilities of existing local area networks (LANs) which primarily address the needs of non-real-time data traffic are reviewed. An architecture called Instanet is introduced to support the needs of distributed real-time systems. Instanet incorporates a logically separate channel to arbitrate on the access rights of different priorities of traffic. An overview of the Instanet architecture is given, and analytical and simulation results of its performance under different traffic loadings are presented.< >

In general, robots are perceived as highly sophisticated devices with something of a science fiction aura and relating little to the more mundane world of industrial automation.

Personal microcomputers, having already made a very significant impact on business and data processing applications of computing, are now showing considerable potential in the automation of simple laboratory tests.

Historically, computer control of processes and experiments has been the domain of large scale industry and research organizations. For small quantity or ‘one off’ systems, the availability of the microprocessor and associated LSI and MSI logic components have lowered the cost of such automation and process control systems by perhaps an order of magnitude. In the case of large quantities, the cost reduction figures are much more dramatic, particularly where the system is realized on a specialized customized VLSI chip. Microprocessor control systems can be realized in a number of ways. This paper explores the conditions and environment in which a personal computer, such as the Commodore PET, can offer lower costs and simpler software and hardware development than systems designed from micromodules i.e. sets of printed circuit boards each performing a specific function.

This paper describes the development of a new microprocessor controlled instrument for use in scoring the Farnsworth Munsell colour vision test. In the test the colour spectrum from red to violet is covered with 85 caps each containing a disc with a slightly different shade. The subject is given caps in random order and is required to rearrange them in colour sequence. The instrument incorporates an M6800 microprocessor which identifies the location of each cap, computes the error score and drives a circular chart recorder. All software for the instrument is written in PL/F, a high level language for microprocessors developed at Strathclyde.

In optical methods of stress analysis, the reduction of raw data to engineering quantities has proved to be a difficult problem. A portable instrument has been developed which interrogates a specimen grid point-wise using a narrow beam of coherent light, and electro-optically measures interference-fringe-spacing, in three directions simultaneously. A microprocessor is incorporated to convert the strain component values to convenient quantities such as principal stress and shear, and these are displayed. The read-rate is adjustable up to 5 kHz, the discrimination level is 4 µε, and a facility for temperature compensation is included. The logic behind the design of the major features of the unit are described.

This paper describes a class of protocols, based on the principle of Timed Packet Release-or TPR, which provide access to high speed local area network bus structures. The principle behind TPR is a system of time delays in the nodes, reckoned from a common timing reference signal generated at a suitable point on the bus structure. By arranging for the delays in each node to increase according to its physical location on the bus nodes always detect packets from "upstream" nodes before their time delay expires. The TPR protocols described in this paper operate on linear bidirectional and unidirectional buses-although the TPR principle can be realised in a number of versions to provide collision free, prioritised, deterministic access to various bus topologies including hub/star. A comparative evaluation of their performance with established methods of bidirectional bus access such as token passing and the reservation protocols is obtained using discrete event simulation. Performance is measured in terms of the average delay-throughput characteristics of the protocols at data rates extending into the Gigabits/sec. region.