A novel on-chip testability access architecture provides comprehensive tester-driven access to the Alpha 21264 microprocessor's testability features during manufacturing. It also allows simple automatic chip-initiated access that leverages the same features during normal chip operation. The architecture uses the IEEE Std 1149.1 to access all test features by creatively solving a number of problems in accessing the chip's at-speed testability features from an asynchronous test port and slow tester.

Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.