The incapability to lower the subthreshold swing (SS) to less than 60 mV/decade is a major obstacle to the scaling down of traditional Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Because of its low SS (< 60 mV/dec), low OFF-state leakage, and high ION/IOFF switching current ratio, the Tunnel Field Effect Transistor (TFET) is one of the prospective substitutes for the traditional MOSFET to overcome this limitation. Furthermore, TFET functions as an energy-efficient switch because of its low power consumption. However, ambipolarity and low ON current are issues with TFET. The term "ambipolarity" describes the TFET's dual nature. The ambipolar problem prevents the TFET from being fully turned off for zero gate bias. Thus, its usefulness and viability in complementary digital circuits are limited. There are several engineering techniques to suppress ambipolarity. This work reviews several device approaches to reduce the ambipolarity of TFET.

This paper presents a comprehensive study on the mapping of stress and strain in FinFETs and explores its implications for device performance. The investigation focuses on the characterization of stress and strain distribution in three-dimensional FinFET structures using advanced modeling and simulation techniques. The impact of stress and strain on device parameters such as carrier mobility, threshold voltage, and overall performance is analyzed in detail. The study highlights the importance of understanding the spatial distribution of stress and strain in FinFET devices and its influence on device behavior. Insights gained from this research can help in the optimization of FinFET design and fabrication processes to enhance device performance and reliability.

Electronic devices made with wide band gap materials are useful for High-temperature applications. GaN and its alloys have proven to be the best choice for high-power microwave applications due to their superior material properties. The excellent thermal conductivity of GaN-based High Electron Mobility Transistors (HEMTs) has attracted researchers to investigate its suitability in high-temperature applications. In this paper, we have analyzed the AlGaN/ GaN HEMT device performance at different temperatures up to 200 degrees C through simulation using the TCAD tool Silvaco Atlas. The variation in device performance (DC and AC) was studied by considering the modification in device parameters and by applying proper device physics. This study will be helpful to the researchers in predicting the HEMT device reliability in high-temperature RF applications.

The breakdown voltage (BV) and specific on-resistance (Ron;sp) are always major concerns associated with the devices used for high-power applications. In this work, a novel doping pillar vertical superjunction high electron mobility transistor (DP-SJ HEMT) with composite pillar structure is designed and simulated using TCAD tool. A gradient doping profile of n-pillar structure is carefully chosen to optimize the BV and Ron;sp. The simulated results in terms of transfer characteristics, transconductance, distribution of electric field and ON-state potential profile are also investigated. The BV and Ron;sp of the proposed device are found to be 8.05 kV and 4.0 mΩ cm2 respectively. It provides a reduction of around 5

GaN-based vertical superjunction high electron mobility transistors (HEMT) are recent avenues for power transistors. In this work, an enhancement mode vertical superjunction GaN-HEMT with gradient doping (GDP-SJ HEMT) is proposed and analyzed. In the GDP-SJ HEMT, the n-pillar doping concentration increases in a gradient manner from top to bottom. Whereas the concentration of the p-pillar is uniform and equivalent to the doping of the middle of the n-pillar. By optimizing the device design and doping profile, the specific-on resistance (Ron,sp) of the device has been reduced from 5.0 m omega-cm2 to 3.79 m omega-cm2. To the best of our knowledge, the frequency performance of vertical SJ HEMT has not been documented in the literature. As a result, we also performed a frequency study. The cut-off frequency (fT) of the proposed device is 78 MHz and the maximum frequency (fMAX) is 71 MHz. The device optimization increases the fT by 89% i.e. 148 MHz and fMAX by 67% i.e. 119 MHz.

Strain engineering has proven to be a useful technique for enhancing the performance of many modern-day transistors. Stress engineering can also have a non-trivial effect on the performance of GaN HEMTs, which are devices of choice for high-power, high-frequency microwave applications. Process-induced stress can have a significant effect on AlGaN/GaN HEMT electrical characteristics in addition to the growth-induced strain present due to lattice constant mismatch between device layers. Understanding the true impact of process-induced strain on AlGaN/GaN HEMT microwave performance is highly necessary. This is especially the case for nonlinearity effects which affect the high-frequency performance of the device. To the best of our knowledge, there is no systematic report on the effect of nitride passivation-induced stress on AlGaN/GaN HEMT device linearity. This work uses a systematic combination of TCAD process simulation and device simulation to quantify the effect of process-induced stress on the device's linearity. This work demonstrates that nonlinearity effects can be minimized through proper tuning of stress by varying design-dependent parameters such as the nitride layer thickness. The effect of stress on highly important linearity parameters of the device like gm, gm2, gm3, VIP2, VIP3, IIP3 and IMD3 is investigated in detail. Comparing the compressive-stress device to the no-stress and tensile-stress devices, we conclude that the compressive stress device has a max gm2 value that is 61% and 71% higher respectively. The max gm3 for compressive stress is 0.13 A V-3 whereas those for no-stress and tensile stress are 0.067 A V-3 and 0.045 A V-3 respectively. However, the voltage-variations of VIP2, and the VIP3 parameters which are derived from these gm values shows that the compressive stress case can help achieve overall better device linearity by stress tuning. This work also studies how the effect of process-induced stress on device linearity varies with the crucial gate length parameter.

The dc performances of FinFETs and NSFETs considering the stress effects using fully-calibrated technology computer-aided design (TCAD) simulations are investigated. The impact of stress on the electrical performances of FinFET and stacked NSFET at sub-7 nm technology nodes are analyzed. It is found that the stacked NSFETs have larger compressive stress due to wider effective channel width which improves the carrier mobility. The simulation results predict that the stress effect strongly influences the stacked NSFET with 29

In this paper, we have reported low-power cache memory with DFT and scan chain techniques utilizing RTL to GDS (Register-Transfer Level to Graphic Design System) implementation in the Cadence Innovus tool using 45 nm technology. In the frontend design, the gate level synthesis is carried out using the Cadence Genus tool with input files i.e., the Verilog file, design constraint, and library file which also generates the gate level netlist file. In the backend design, the physical design implementation is proposed including different intermediate levels such as synthesis, placement, routing, and timing analysis to optimize the design in terms of power, timing, and area. We have proposed a low-power cache memory including a clock gating technique to reduce the dynamic power consumption. It is estimated that the total power consumption of the proposed Low Power Cache Memory design is 20% less than the standard cache memory design. We have studied the superflow, a fully customized RTL to GDS design flow tailored for low-power cache memory, and also reported power and timing analysis. This paper emphasizes the importance of each stage in the ASIC design cycle, highlighting every phase-starting from design specification, architecture design, RTL coding, synthesis, place and route, and verification-plays a critical role in shaping the final performance with ample opportunities for future research optimizing the design for enhanced performance.

The electron-optical properties like I-V characteristics, luminous power, power spectral density (PSD), and full-width half maxima (FWHM) of an InGaN/GaN multiple quantum well-based LED are analyzed using the Silvaco TCAD tool. It is shown that the anode voltage vs. anode current shows a general PN junction characteristic with a threshold voltage 4.5 V and delivers a 150mA anode current at 6.5 V. The luminous power enhances linearly with anode current and it is supported by the electron concentrations in the wells of the MQW. The results on PSD reflected that it also increases with enhanced anode voltage and shows better performance as compared to that of conventional single QW-based LED. The discussed results will be helpful in improving the internal quantum efficiency of the conventional LED/LASER structures along with unipolar laser-like QCL. A high-efficiency MQWs LED with InGaN as a well and GaN barrier is designed and analyzed.

The double-hetero GaN/AlGaN/GaN polarization junction (PJ) is a semiconductor structure designed to enhance the performance of RF (Radio Frequency) and power devices, primarily based on wide band gap materials like GaN (Gallium Nitride). By incorporating a GaN/ AlGaN/GaN structure, the device can create two-dimensional hole gas (2DHG) and two-dimensional electron gas (2DEG) at the upper and lower junctions, respectively. The PJ takes advantage of the inherent polarization properties of GaN and AlGaN materials. In AlGaN layer the Al composition is graded from 1% to 23% to improve the DC and RF characteristics. The composition grading improves the Gm by 37.6% and the output drain current by 51%. The cut-off frequency and maximum frequency also improve.

Gate-all-around Nanosheet field-effect transistor (GAA-NSFET) is a potential replacement for the state-of-art FinFET devices at advanced technology nodes. In this article, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using 3D TCAD numerical device simulation is studied. The WFV of NSFETs and NWFETs using multiple stack channels are also analyzed. The fluctuation in the threshold voltage (σV TH ) and on-current (σI ON ) of NSFETs is mainly affected by the WFV of the metal gate. It is investigated that single and 3-stacked NSFET shows superior immunity to WFV compared to NWFET. Furthermore, a layout-based NSFET inverter design using the DTCO technique is followed and the advantages of the stacked NSFET in terms of delay, power dissipation and switching energy are also reported.

The double-hetero GaN/AlGaN/GaN polarization junction (PJ) is a semiconductor structure designed to enhance the performance of RF (Radio Frequency) and power devices, primarily based on wide band gap materials like GaN (Gallium Nitride). By incorporating a GaN/ AlGaN/GaN structure, the device can create two-dimensional hole gas (2DHG) and two-dimensional electron gas (2DEG) at the upper and lower junctions, respectively. The PJ takes advantage of the inherent polarization properties of GaN and AlGaN materials. In AlGaN layer the Al composition is graded from 1% to 23% to improve the DC and RF characteristics. The composition grading improves the Gm by 37.6% and the output drain current by 51%. The cut-off frequency and maximum frequency also improve.

Stress/strain engineering techniques are employed to boost the performance of Gate-all-around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7 nm technology nodes and beyond. In this work, we report on the 3D numerical simulation study of the impacts of source/drain epitaxial and uniaxial strained-SiGe channel stresses on p-type NSFETs. It is shown that the uniaxial strained-SiGe channel improves the drive current by up to 107% due to higher compressive stress while the 3-stack NSFET can achieve an enhancement in drive current even up to 187% using a 30% Ge mole fraction. Furthermore, we compare the multiple stacked channel NSFETs and nanowire FETs (NWFETs) considering different strain techniques. As compared to a 3-stack strained-SiGe NWFET, NSFETs show 27% and 10% enhancements in I-ON and SS, respectively. Vertically stacked NSFETs are shown to be the best option to improve the hole mobility under biaxial and uniaxial compressive strain rather than NWFETs. We also look at how the Ge mole fraction affects various electrical properties in a uniaxial strained-SiGe channel with shrinking dimensions of scaled NSFETs. It is observed that for a fixed L-g, I-ON/I-OFF ratio, SS and DIBL decrease with the increase in Ge mole fraction.

AlGaN HEMTs are popular devices for high-frequency applications. At higher frequencies, nonlinearity effects are major concerns and need serious attention. In this work, we have attempted to improve the linearity performance of graded channel Al x Ga 1− x N/GaN HEMTs in comparison with abrupt channel GaN HEMTs through Technology Computer Aided (TCAD) simulation. In graded channel HEMTs, linearly grading of Al composition in the AlGaN layer, reduces the local carrier densities and provides improvement in the carrier saturation velocity. This provides an avenue to improve the overall linearity performance. A complete set of figures of merits (FOMs) such as g m 2 , g m 3 , VIP 2 , VIP 3 , IIP 3 and IMD 3 for both devices are presented. The simulation results have been calibrated with reported experimental results available in the literature. The graded devices are observed to have better transconductance ( g m ) and drain current for gate voltages greater than −2 V. The drop in g m is reduced by nearly 50% at the higher gate-to-source voltages. Moreover, the RF figure of merits such as the current gain cutoff frequency ( f T ) and a maximum frequency of oscillation ( f max ) have been calculated for both devices. Due to the graded channel f T increases by 20% and f max becomes twice which makes it a better choice for high-voltage and high-power applications. The impact of interface trap and leakage current performance on the graded channel device are also reported. The cutoff frequency reduces by 25% with an increase in trap charge concentration from 9e17 cm −2 to 1e19 cm −2 . Also, it has been found that the graded channel device shows better linearity and lower intermodulation distortion in comparison to the abrupt device which has been calculated from the linearity parameters. The high gate leakage current in the case of the graded channel device can be reduced by adding a thin GaN cap layer on the AlGaN channel which can be a future prospect of improving the performance of the graded GaN device.

Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are a potential replacement for the state-of-the-art fin field-effect transistor (FinFET) devices at advanced technology nodes. In this paper, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using three-dimensional technology computer-aided design numerical device simulation is studied. The WFVs of NSFETs and nanowire field-effect transistors (NWFETs) using multiple stack channels are also analyzed. The fluctuations in the threshold voltage (& sigma;V (TH)) and on current (& sigma;I (on)) of NSFETs are mainly affected by the WFV of the metal gate. It is observed that single and three-stacked NSFETs show superior immunity to WFV compared with NWFETs. Furthermore, a layout-based NSFET inverter design using the design technology co-optimization technique is followed, and the advantages of stacked NSFETs in terms of delay, power dissipation and switching energy are also reported.

Strain engineering has proved to be useful for enhancing the performance of AlGaN/GaN HEMT devices. The device transfer characteristics are significantly affected by proper optimization of the stress in the nitride passivation layer. Nonlinearity effects are the major concern for AlGaN/GaN HEMT devices at high frequencies which can vary due to the intrinsic stress in the nitride passivation layer. In this paper for the first time, we have reported the effect of stress on the linearity of the device. With L G =200nm the linearity parameter like g m1 , g m2 , g m3 , VIP 2 , VIP 3 and IIP 3 are compared for no stress, comparative stress and tensile stress device.

Pseudomorphic high-electron mobility transistors (PHEMTs) are one of the foremost choices for nextgeneration high-power devices for power and RF applications. In this work, a $3 \times 25 \mu \mathrm{m}$ recessed gate pseudomorphic AlGaAs/InGaAs/GaAs is designed and simulated. The DC and AC performances are precited with key performance indicators such as transconductance, capacitance, transit frequency and maximum oscillating frequency respectively. From the DC analysis, maximum transconductance $\left(g_{m}\right)$ is found to be 142.28 $\mathrm{mS} / \mathrm{mm}$ with $\mathrm{I}_{\mathrm{DSS}}=\mathbf{0. 4 1 8 \mathrm { A }}$. The cut-off frequency (f T) and improved maximum oscillating frequency ($f_{\max }$) are found to be 70 GHz and 400 GHz respectively. It indicates improved RF performance and suitable applications in microwave and RF applications.