This paper describes a multi-rate synchronizer that makes use of a polyphase filter bank to simultaneously perform matched-filtering and interpolation to correct for symbol timing offsets observable on a sampled-data receiver. Interpolation between available sample points is achieved by selecting the appropriate filter in the bank which provides the optimal sampling time. Furthermore, carrier phase error is corrected by adding a second control loop to drive a numerically-controlled oscillator before matched filtering, mitigating distortion caused by any carrier offset. This design is tractable for burst-mode transmissions where symbol timing and carrier frequency/phase acquisition is nec- essary for each data frame and allows for symbol timing and carrier offset estimators to be used in conjunction with the loop control architecture provided. Simulations under various timing and carrier impairments are provided. I. INTRODUCTION

—This paper describes a multi-rate synchronizer thatmakes use of a polyphase filter bank to simultaneously performmatched-filtering and interpolation to correct for symbol timingoffsets observable on a sampled-data receiver. Interpolationbetween available sample points is achieved by selecting theappropriate filter in the bank which provides the optimalsampling time. Furthermore, carrier phase error is corrected byadding a second control loop to drive a numerically-controlledoscillator before matched filtering, mitigating distortion causedby any carrier offset.This design is tractable for burst-mode transmissions wheresymbol timing and carrier frequency/phase acquisition is nec-essary for each data frame and allows for symbol timing andcarrier offset estimators to be used in conjunction with the loopcontrol architecture provided. Simulations under various timingand carrier impairments are provided. I. I NTRODUCTION Software-defined radios (SDR) aim to move as much digitalsignal processing (DSP) as close to the antenna as possible,creating a flexible architecture for reconfiguration and adapt-ability. As a result, SDR provides a versatile platform unavail-able to analog systems. Synchronous data communicationssystems on SDR platforms rely on DSP algorithms to correctfor symbol timing and carrier phase impairments observableat the receiver. Physical layer synchronization of symboltiming is required when samples of the received signal aremisaligned with the data symbols generated by the transmitter.Several options to align the matched filter output samplesare available; signal filtering, however, consumes a significantportion of baseband processing, and, as a result, oversamplingthe received signal in excess of the Nyquist rate is undesirable.Alternatively, interpolating between available sample pointsproves to be computationally efficient. Furthermore, the useof a polyphase filterbank as an effective phase shifter in thesampling clock allows for greater flexibility and efficiency inthe receiver by computing only those multiplications necessaryfor matched filtering while simultaneously interpolating toachieve a sample point sufficiently close to the optimum.Rice and Harris proposed the use of polyphase filter banksfor symbol synchronization in digital receivers in [1] anddeveloped loop control architectures for choosing the optimalfilter in the bank. This paper extends their work by addingan additional control loop for carrier synchronization aftermatched filtering. A numerically-controlled oscillator placedbefore matched-filtering the received signal ensures that pulsedistortion due to input carrier offsets is minimized. Thisdesign allows for simultaneous tracking of both symbol timingand carrier phase mismatches and is particularly tractablefor burst-mode duplexing schemes where carrier phase andsymbol timing acquisition needs to be performed on eachtransmission burst. The loop architecture described in thispaper incorporates coarse frequency and symbol timing offsetestimators in a natural way, however the discussion is limitedto tracking mechanisms and assumes acquisition of timing andcarrier frequencies has been established.Carrier phase synchronization before matched filtering canbe corrupted by out-of-band noise and adjacent-channel in-terference, however matched filtering before decimating canconsume valuable processing resources. This motivates aninvestigation on alternative techniques that combine the twointo a single processing block with independent control loops.Common concerns issued to systems operating with two feed-back loops can be avoided by realizing that the timing recoveryalgorithm operates independently of the input phase, so longas the input carrier frequency offset remains sufficiently small.Issues with carrier loop perturbations due to tracking beforetiming synchronization is achieved is also addressed.The system was implemented in C++ with minimal third-party software dependencies. Over-the-air testing was per-formed using Virginia Tech’s open-source SCA implementa-tion [2] by wrapping the multi-rate synchronizer DSP insidea set of SCA components.This paper is organized as follows: Section II gives abrief theoretical background on multi-rate synchronization anddiscusses the efficacy of using polyphase filterbanks as amechanism for calculating interpolants; section III discussesthe proposed loop control architecture for combining timingand carrier phase synchronization; section IV describes thesimulations used in evaluating the system; section V givesnotes on its implementation in an SCA platform; Finally,section VI gives some brief concluding remarks.II. M