The manufacturability and reliability of wirebonds depends on many factors, most of which are linked to the BEOL wafer fabrication process. This paper presents a detailed experimental analysis of the effect of pad thickness and liner levels on the quality of the interconnection. Varying ball sizes are evaluated and compared for different target pitch applications. Thermal aging of the wirebonds with subsequent wire pull and ball shear was studied and the challenges of this test are described.

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

We previously proposed a method to control the downlink packet flow at the base stations of CDMA wireless networks where we maximize data throughput while ensuring fairness among users. In this work, we investigate important issues for realistic implementations. Firstly, we evaluate the network performance when cell subdivision into zones is used for the purpose of complexity reduction. We show up to 50% reduction, for a minimal loss in total throughput. Secondly, a modified algorithm is proposed to support multi-class users. The results provided show that priority for distant users requesting high data rates can be maintained with no significant decrease in total throughput. Finally, the compromise between short-term fairness ensured by our algorithm and long-term fairness taking benefit of mobility is also studied.

As density of VLSI devices continues to increase at a rapid rate, extensive efforts are being made in development of fine pitch wirebond for IC packages to utilize higher I/O counts while shrinking chip sizes. With the small size of ball bonds required for recent fine pitch wirebond applications, the effect of the probe mark under the wirebond ball is becoming a major concern for a manufacturable assembly process.This paper consists of two portions: a characterization of the current situation and an introduction with experimental analysis of possible solutions.In the first section, the relationship between probe mark size/depth and the wirebond integrity was evaluated. The evaluation results conclude that the percentage of probe mark area deeper than 0.6um must be limited to 25-30% of the ball bond area to achieve reliable ball bonding.Wafer test however is under continuous pressure to achieve maximum yield results, which often leads to an increase in probe hit frequency and probe mark size. These two conflicting interests are an increasing problem as pad pitch decreases. Conventional Al pads with traditional wirebonding methods will soon be challenged beyond their capabilities if we continue to follow ITRS roadmap. In the second part of this paper, several novel possible pad solutions were investigated and experiments were performed at wafer test and wirebonding.