By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents an improved scheme for generating pre-computed test patterns in core-based systems on chip. This approach reduces the number of pre-computed test patterns and as the result, test application time (TAT) will be decreased. Experimental results on ISCAS'89 benchmark circuits show improvement in the number of test clock cycles.

Sequential circuit testing has been recognized as one of the most difficult problems in the area of fault detection. Controllability and observability of a sequential circuit is low because of their internal states. Therefore finding suitable sequence of test patterns is becoming increasingly complex. We have proposed a method to estimate an expectation graph by utilizing a mathematical model which exploits probabilistic 4-value system. The expectation graph is used to determine the minimum number of faults detected by a suitable sequence of test patterns. Experimental results show our mathematical model has reduced number of test patterns in specified fault coverage.