Artificial intelligence (AI) accelerators are vital for efficiently executing data-heavy workloads, but increasing design complexity and shrinking manufacturing processes introduce serious reliability challenges, including silent data corruptions (SDCs). While CPU reliability has been analyzed significantly, AI accelerators require tailored analysis due to their diverse and evolving designs. We present Phoebe, a comprehensive methodology for evaluating the reliability of systolic array-based AI accelerators harnessing the power of microarchitectural modeling. Phoebe captures the full compute stack, from software to gates, across diverse design points, including dataflows, datatypes, memory hierarchies, and array sizes. We support statistical fault injection on key hardware structures-such as static random-access memory, registers, and functional units-across multiple fault models. Phoebe also incorporates acceleration techniques that increase injection throughput by more than 1000 & times; without sacrificing accuracy. Evaluations on diverse machine-learning models reveal SDC vulnerability trends across accelerator design points, demonstrating Phoebe's effectiveness for broad design-space exploration.

Hardware defects that evade manufacturing testing have emerged as a key concern, with multiple reports from hyperscalers pointing to marginal defects as a root cause for silent data corruptions (SDCs) at scale. Functional testing - where a CPU executes native instructions in its regular operating mode - is a popular approach that can be deployed on demand or periodically in large scale fleets. Functional testing must: (a) reproduce the physical operating conditions that activate marginal defects, and (b) expose the resulting microarchitectural faults by exercising relevant hardware structures and propagating their effects to architectural state. Harpocrates is a recently proposed functional testing approach providing automated generation of high quality functional test programs. By leveraging the speed and visibility of microarchitecture simulation, Harpocrates achieves high structural coverage of the targeted hardware components and ensures propagation of microarchitectural fault effects to architecturally observable state. This paper applies the Harpocrates methodology to the practical detection of marginal hardware defects in modern CPUs that are known-defective. We show how specific operating conditions activate marginal defects, and how deliberate manipulation of these conditions enables functional tests generated by Harpocrates to reliably expose failures. We also extend the baseline methodology to include delay-related fault models. Beyond demonstrating successful fault detection, this work exposes the practical challenges of testing for marginal defects in modern CPUs. The resulting insights generalize beyond the specific defects studied and inform the design of future functional testing methodologies for marginal hardware.

Multicore CPUs typically share the Last-Level Cache (LLC) across cores, leading to interference between co-executing workloads with significant performance and security implications. Page coloring has emerged as an effective software mechanism for LLC partitioning. Simultaneously, virtual memory enables fundamental abstractions, but incurs increasing performance overheads due to address translation. Huge pages alleviate this issue by expanding TLB reach, thereby reducing TLB misses and the associated costly page table walks. However, these two techniques are considered mutually exclusive, since huge pages span all LLC sets, precluding coloring.In this paper we introduce Colored Huge Pages (CHP), a hardware-software co-design that enables the simultaneous use of page coloring and huge pages. By distributing the physical frames of a virtually contiguous huge page across physical memory in a predictable strided pattern, our design allows coloring of the individual pages while preserving the TLB reach and translation efficiency of conventional huge pages. On the software side, we modify the OS allocator to construct colored huge pages by extracting appropriately colored pages from larger physical blocks and caching leftover mappings for future use. On the hardware side, we extend the L2 TLB to efficiently translate these mappings by leveraging their regular structure. We implement our approach in a recent Linux kernel and evaluate it using memory intensive workloads. CHP mitigates LLC contention and address translation overheads, improving performance by 33.7% compared to using 4 KB pages without LLC partitioning, requiring only minimal OS and architectural modifications. Contrary to prior approaches, our proposal maintains comparable effectiveness under fragmentation, avoids inducing additional cache misses, and incurs only negligible page fault overhead relative to Transparent Huge Pages (THP).

Hardware faults in AI accelerators may corrupt intermediate tensor values during inference; when these corruptions propagate to the final model output without detection, they result in silent data corruptions (SDCs). Existing protection techniques often rely on software-level fault injection or model-level heuristics, which can miss how faults are actually exposed, propagated, and amplified by accelerator microarchitecture. In this work, we use microarchitecture-level fault injection to analyze the cross-layer manifestations of hardware-induced faults in modern neural network architectures based on Transformers. By instrumenting ONNX Runtime, we observe intermediate tensor outputs at accelerator and runtime boundaries and classify the numerical symptoms that precede output-level SDCs, including Nan/Inf values and out-of-range tensors. This analysis identifies which fault effects are visible to lightweight runtime checks, where such checks are likely to be most effective, and where simple numerical symptoms are insufficient. Overall, the study exposes hardware-informed protection opportunities for future low-cost runtime resilience mechanisms.

Several hyperscalers have recently disclosed the occurrence of silent data corruptions in their system fleets, sparking concerns about the severity of known and the existence of unidentified root causes of faults in CPUs. These incidents reveal that CPUs may generate incorrect results due to latent manufacturing defects, variability, marginalities, bugs, and aging. To tackle this, we present Harpocrates, an automated methodology for the generation of short, constrained-random functional test programs that maximize fault detection in target CPU structures and can be employed at different stages of the system lifecycle. Harpocrates adopts a hardware-model-in-the-loop approach, iteratively refining the generated test programs via a detailed simulation-based microarchitecture engine that models and grades for multiple fault types. Harpocrates adapts to various program generators, instruction set architectures, microarchitectures, and fault types. Our results on seven important CPU structures show that Harpocrates outperforms open source test suites in fault detection capability while attaining much shorter generation times.

As semiconductor fabrication scales to smaller technology nodes, process variation presents significant challenges, affecting power consumption, thermal behavior, and voltage stability in silicon compute devices. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage is a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, the AMD GPU side remains relatively unexplored. Process variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability by combining undervolting characterization with neutron irradiation physical experiments, contributing to a deeper understanding of undervolting and resilience of AMD GPUs.

Compute-in-Memory (CiM) architectures based on non-volatile memories (NVMs) promise substantial performance and energy benefits by mitigating the memory wall through near-memory, massively parallel computation. However, NVM-CiM designs suffer from intrinsic reliability challenges caused by process variations, analog sensing of resistive states, imperfect reference levels, and reduced sense margins as operand count increases. These effects lead to overlapping output distributions and decision failures at the sense amplifier level, which accumulate across large applications and undermine end-to-end correctness. In this work, we propose a software–hardware co-design approach to ensure application-level reliability in NVM-CiM systems. Our method employs double-reference sensing to flag potential decision failures during CiM execution and records potential errors using a lightweight error-flag mechanism. Flagged outputs are selectively recomputed on the CPU, correcting errors while preserving the benefits of CiM execution. We quantify decision failure probabilities for different sense amplifier designs, study optimal reference placement, and quantify application-level reliability, comparing CiM execution with a CPU-only baseline. Results show that by optimizing the double referencing design, fewer than 1% of outputs require correction on average, achieving application-level decision failure rates below 10−12. Despite introducing about 1% runtime and energy overhead, the proposed method remains significantly more efficient than CPU-only execution, enabling reliable and practical deployment of NVM-CiM architectures.

Hyperscalers have reported unexpectedly high numbers of defective CPU chips, with a defect rate of 1 in a 1000, leading to Silent Data Corruptions (SDCs) in their computing fleets. However, there is no public data on the rate of SDC incidents (corrupted program executions) in large fleets, nor nor any detailed information on which CPU units, microarchitectures, or workloads are more likely to generate SDCs due to silicon defects. While CPU array structures have been studied for fault effects, arithmetic units like integer and floating-point units have not been thoroughly analyzed as potential root causes of SDCs. This paper addresses this critical gap by accurately modeling hardware faults in the arithmetic units of modern x86 CPUs and measuring the probability and rates of SDCs. Using a full-system gem5-based fault injector, the paper examines SDC trends across five recent $x 86$ microarchitectures, various arithmetic units, and instruction classes. By integrating real-world defect rates from large-scale datacenter experiments with early-stage modeling and simulation, the paper provides critical insights into SDC incident rates across different systems. This information is essential for guiding hardware-based or software-based fault protection methods and is the paper’s primary contribution to minimizing the impact of silent data corruptions in computing.

Compute-in-Memory (CiM) employing Non-Volatile Memory (NVM) technology is an emerging paradigm that promises higher power efficiency for important data-intensive computations. The performance, power, and resilience properties of emerging NVM technologies determine the efficiency of architectures built around processors and computational memories, and affect design decisions. Thus, fast exploration of the broad design space is necessary to assist decision-making. We present Sisyphus, the first cross-layer framework built to facilitate computer architecture research when such an exploration is required. Sisyphus incorporates detailed technology information for various CiM circuit designs based on STT-MRAM, ReRAM, and PCM technologies and integrates them in fast microarchitecture level system models in gem5 to evaluate performance, power, and resilience (through fault injection) across a large space of design options. Sisyphus’ holistic modeling enables the comprehensive evaluation of all efficiency aspects during the execution of actual workloads on the CPU-CiM architecture. This allows for comparisons to a baseline CPU-only system. In our experimental evaluation, we demonstrate how Sisyphus can derive conclusions regarding the prevalence of one NVM type over another, depending on the prioritized optimization aspect(s).

Serverless computing has emerged as a competitive cloud computing paradigm. At the same time, the open-source RISC-V ISA has gained a lot of interest and the first RISC-V systems have already started to appear in the server market for datacenters. The combination of these computing trends necessitates the performance assessment of the impact of the RISC-V ISA and relevant processor implementations when executing serverless workloads. However, currently there is no benchmarking support for systematically evaluating serverless workloads on RISC-V systems. In this paper we bridge this gap in benchmarking support across the layers of the computing stack, from the application to the microarchitecture. We port the vSwarm serverless benchmark suite to the RISC-V ISA and enable the execution of the workloads in both real and simulated RISC-V platforms using the gem5 microarchitectural simulator. To demonstrate the usefulness of the infrastructure, we quantify the performance trade-off of cold vs. warm execution on a simulated RISC-V system and validate the results against a real platform. Overall, our enhanced benchmarking support creates new opportunities for further experimentation with serverless workloads on RISC-V systems, enabling the analysis and optimization of their performance across the computing stack.

Silent Data Corruption (SDC) is the most severe effect of a silicon defect in a CPU or other computing chip. The arithmetic units of a CPU are, usually, unprotected and are, thus, the ones that most likely produce SDCs (as well as visible malfunctions of programs such as crashes). In this work, we shed light on the traversal of silicon defects from their point of origin deep inside arithmetic units of complex CPUs towards the program result. We employ microarchitecture-level fault injection enhanced with gate-level designs of the arithmetic units of interest. The hybrid setup combines (i) the accuracy of the hardware and fault modeling and (ii) the speed of program simulation to run long programs to end (thus observing SDC incidents); the analysis that this combination delivers is impossible at other abstraction layers which are either hardware-agnostic (software level) or extremely slow (gate-level). We quantify the effects of faults in two stages and with multiple metrics: (a) how faults propagate to the outputs of the arithmetic units when individual instructions are executed, and (b) how faults eventually affect the outcome of the program generating SDCs, crashes, or being masked. Our fine-grain findings can be utilized for informed fault detection and tolerance strategies at the hardware or the software levels.

Programmable AI accelerators become increasingly important to modern computing infrastructure, thus, their reliability is critical for the integrity of the produced results. Silent Data Corruptions (SDCs)-incorrect program outputs that occur without any warning or notification-have been reported by hyperscalers such as Meta, Google, and Alibaba, affecting both CPUs and AI chips in production environments. SDCs originate from a range of low-level causes including manufacturing defects, aging-induced degradation, process variation, particle strikes, and electromagnetic interference. In this work, we revisit the modeling debate between software-level and microarchitecturelevel fault injection for estimating SDC vulnerability, in the context of programmable AI accelerators. While software-level (hardware agnostic) techniques are fast and easy to deploy, studies on CPUs and GPUs have shown they produce misleading results due to their lack of the hardware notion which determines faults propagation or filtering. We show that these issues also persist dramatically in AI accelerators. Using detailed microarchitectural modeling, we demonstrate that even so-called hardware-aware software-level approaches can misestimate FIT rates by more than 4x across realistic accelerator configurations. Our findings support microarchitecture-level simulation as the most effective tradeoff point between accuracy and scalability for early-stage reliability analysis of programmable AI hardware.

Cache memory reliability is a critical concern in modern processor architectures, particularly in systems deployed in fault-prone environments or at large scale. As modern computing systems increasingly rely on cache memories for performance, ensuring their reliability against transient faults (soft errors) is crucial. Several protection schemes, such as parity or error-correcting codes (ECC), have been proposed to enhance cache robustness. However, these techniques introduce trade-offs in terms of performance and effectiveness, which are particularly relevant in RISC-V-based CPUs due to their flexibility and modular design. This paper presents a comprehensive characterization and design space exploration of error protection mechanisms (parity and Single Error Correction Double Error Detection - SECDED - ECC) in the cache memories of RISC-V CPUs. We employ statistical fault injection at the microarchitecture level to evaluate the impact of transient faults on system reliability, analyzing their effects across system layers in a full-system setup using the gem5 simulator, the only environment that supports the execution of long workloads. By comparing caches with and without protection, we provide insights into error resilience, overheads, and the effectiveness of protection schemes. Our study can drive the selection of appropriate protection strategies for various RISC- V implementations, ranging from embedded systems to high-performance computing platforms. Our findings offer valuable guidance for the design of robust and efficient RISC- V-based systems operating under reliability constraints.

Vector architectures have re-emerged as a key component of high-performance computing, offering scalable parallelism for data-intensive workloads. The open and extensible RISC-V instruction set architecture (ISA) further accelerates innovation in this domain, enabling flexible design and exploration of vector processing units (VPUs). In this work, we present the first implementation of an Architecturally Correct Execution (ACE) analysis framework for vector processing units (VPUs) in gem5, demonstrated on a RISC-V VPU model, enabling estimation of failure rates due to transient faults across a broad design space. Our implementation targets the largest (and thus most vulnerable) hardware structures: Vector Register File (VRF), data cache (D-Cache), and L2-Cache, analyzing ACE behavior across various configurations of these components. We conduct experiments using both scalar and vectorized versions of a benchmark suite, tested with multiple input sizes. The goal is to measure the Architectural Vulnerability Factor (AVF) of a VPU design and identify architectural components that are most susceptible to soft errors. Our results demonstrate how vectorization, workload characteristics, and hardware parameters affect ACE behavior, providing valuable insights for improving the reliability of modern VPU architectures.

Silent data corruptions due to defective silicon cause erroneous program results. Yet nobody knows how severe and frequent the problem is, how much we need to invest in solving it, and who should pay the bill.

Accelerating the development of secure and reliable photonic and electronic systems George Papadimitriou and Dimitris Gizopoulos from the University of Athens discuss the value of simulation frameworks in optimizing the development and integration of photonic and electronic systems. Simulation frameworks are indispensable in modern hardware and computing systems development, enabling researchers to evaluate and optimize complex architectures before physical implementation. These tools facilitate detailed modeling of hardware components, interactions, and performance under various workloads – a broad exploration of the hardware and the software design space. For emerging technologies like photonic accelerators, which promise significant speed and energy efficiency improvements, simulation offers a controlled environment to analyze designs and refine them for real-world applications before expensive physical design takes place.

As semiconductor fabrication scales to smaller technology nodes, process variation has become a significant challenge, affecting power consumption, thermal behavior, and voltage stability in microprocessors and GPUs. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage, while maintaining a fixed frequency, has emerged as a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, AMD GPUs remain relatively unexplored, particularly in terms of process variation. This variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability under undervolted conditions, highlighting the impact of chip-to-chip variability. Our findings contribute to a deeper understanding of undervolting in AMD GPUs and its dependence on process variation, providing insights into practical power-saving strategies.

In this work, we discuss our vision for neuromorphic accelerators based on integrated photonics within the framework of the Horizon Europe NEUROPULS project. Augmented integrated photonic architectures that leverage phase-change and III-V materials for optical computing will be presented. A CMOS-compatible platform will be discussed that integrates these materials to fabricate photonic neuromorphic architectures, along with a gem5-based simulation platform to model accelerator operation once it is interfaced with a RISC-V processor. This simulation platform enables accurate system-level accelerator modeling and benchmarking in terms of key metrics such as speed, energy consumption, and footprint.