The floating body effect (FBE) degrades the retention characteristics of three-dimensional (3D) dynamic random-access memory (DRAM) by increasing the body potential of the access transistor. In this work, retention degradation in 3D DRAM with a gate-all-around (GAA) access transistor is systematically investigated using mixed-mode TCAD simulations. Both dynamic and static retention characteristics for the ‘1’ and ‘0’ states are analyzed as functions of channel thickness (TCH) and channel width (WCH) to assess scaling effects, while explicitly accounting for the quantum confinement effect (QCE). Based on this analysis, the optimal TCH and WCH that balance FBE suppression and on-state current degradation are identified. A duty-cycle-controlled pulse scheme (DCPS) is proposed to quantitatively decouple the FBE-induced retention degradation from quasi-static leakage contributions. In addition, a comparative study of silicon and amorphous oxide semiconductor channels is conducted to elucidate material-dependent FBE and retention mechanisms.
As DRAM technology continues to scale, process-induced chlorine (Cl) contamination has become an important reliability concern because residual Cl near the Si/oxide interface can promote interface defect generation, near-interface trap formation, and cell-level electrical instability. In this work, residual oxide engineering is investigated as a process-compatible strategy to suppress Cl diffusion toward the active silicon region in advanced DRAM structures. Building on prior oxide-based Cl mitigation approaches, this work provides quantitative material and electrical evidence that controlled WOx formation on landing-pad tungsten and intentional residual oxide retention in selected air spacer regions reduce Cl incorporation within the existing DRAM fabrication flow. Chemical and electrical analyses show that increased WOx formation reduces the Cl concentration in the active silicon region by approximately 20%, while controlled residual oxide retention in the air spacer region further decreases Cl incorporation by approximately 51%. The reduction in Cl penetration is accompanied by a corresponding decrease in 1-row distable fail bits, indicating a strong correlation between interfacial Cl incorporation and DRAM electrical reliability. These results suggest that residual oxide engineering can mitigate Cl-associated reliability degradation without increasing process complexity, providing a practical route for improving single-bit failure characteristics in advanced DRAM fabrication.
Electromigration (EM) is an important wearout mechanism for semiconductor circuits. Designers must ensure that interconnect networks do not fail before the required lifetime for the circuit. The design rules given to designers related to electromigration (EM) of interconnects are derived from Black’s model for EM. They are calculated based on empirical experimental data during technology development. Designers have more margin and flexibility if the design rules are based on the more modern physics-based Korhonen model, which accounts for interactions among interconnect segments. This paper demonstrates that the Korhonen model can be calibrated with the same number of wire geometries, current densities and temperatures as Black’s model and explains the calibration procedure needed to extract all relevant parameters. The number of parameters that must be determined for the Korhonen model is reduced from 14 to 4 using the proposed method. The reduced model captures all physical behavior incorporated in the partial differential equations of the Korhonen model. The reduction in the number of parameters simplifies calibration during technology development.
This study systematically investigates the single-pulse surge current capability of 1200 V SiC MOSFETs under various gate bias conditions, and further explores the degradation mechanism induced by repetitive surges. Experimental results demonstrate that the surge current capability varies with the gate voltage, which is attributed to the current through the channel during surge conditions. Meanwhile, under repetitive surges, threshold voltage (VTH) drift and bipolar degradation exert competing effects on the on-state resistance (RDS(ON)) across different gate bias conditions. Subsequent experiments confirm that the variations in VTH are attributed to the degradation of the SiC/SiO2 interface, as further supported by capacitance-gate (CG-VG) characterization after surge stress. Notably, the source-drain voltage drop (VSD) shows a continuous increase due to bipolar degradation caused by repetitive surges, as confirmed by reverse recovery analysis. Overall, this paper provides deeper insights into the performance degradation behavior of SiC MOSFETs under repetitive surges.
Addressing the crosstalk issue in SiC MOSFET half-bridge circuits, this paper establishes a high-accuracy SiC MOSFET capacitance analytical model based on semiconductor physics (R² > 0.99) to characterize the voltage-dependent behavior of Cgd. Embedded into circuit simulations, the proposed model demonstrates significantly superior accuracy compared to traditional fixed-capacitance models in predicting both the amplitude and duration of crosstalk voltage spikes. Parameter sensitivity analysis reveals that Cgd and gate resistance Rg dominate the gate crosstalk mechanism, with Cgs and gate inductance Lg being secondary factors. Based on this mechanism, a mature circuit-level optimization strategy is first implemented, suppressing gate parasitic inductance to Lg = 7 nH and incorporating resistor decoupling. An innovative device-level approach is further proposed, utilizing a mesh-gate structure to increase the Cgs and a split gate structure to reduce Cgd. The device optimization achieves a further 34.2% reduction in gate crosstalk. This study establishes a complete technology chain integrating physical modeling, simulation verification, and circuit-device co-optimization, providing empirically validated design support for crosstalk suppression in SiC power systems.
Heavy-ion-induced single-event burnout (SEB) poses a serious threat to the reliability of β-Ga2O3 power diodes. A unified two-dimensional technology computer-aided design (TCAD) framework is used to compare SEB in vertical β-Ga2O3 Schottky barrier diodes (SBDs), vertical p-type nickel oxide (p-NiO)/n-β-Ga2O3 heterojunction diodes (HJDs), and lateral β-Ga2O3 Schottky barrier diodes (LSBDs), and to distinguish the strike-sensitive location from the final failure location. In the vertical SBDs and HJDs, heterojunction and field-plate engineering increase the static breakdown voltage. However, transient field amplification near the anode edge or another terminal high-field region continues to govern failure, resulting in low SEB thresholds. Among the LSBDs, the structure with a 75 nm p-NiO reduced surface field (RESURF) layer achieves the highest breakdown voltage, exceeding 10 kV through charge balance, but does not provide the greatest SEB robustness. As the p-NiO thickness increases, the sensitive window shifts from the anode edge toward the RESURF region and the p-NiO edge, whereas the final avalanche path remains coupled to the high-field region on the anode side. The structures with p-NiO thicknesses of 97 and 132 nm consequently achieve VSEB/BV ratios of 48.9% and 70.4%, corresponding to SEB derating ratios of 51.1% and 29.6%, respectively. These findings clarify the distinct SEB triggering processes in vertical and lateral devices and provide guidance for radiation-hardened design through coordinated optimization of the static field distribution, sensitive-window location, and carrier-coupling path.
This study investigates NanoSheet FET (NSFET) under the influence of heavy-ion radiation. A single, high-energy particle can alter device's state or inflict temporary or permanent damage commonly known as a Single Event Effect (SEE). In this work, SEE at different incident angles and linear energy transfer (LET) circumstances have been measured in order to look into the radiation profile. Using 3D Sentaurus TCAD, investigation of the NSFET device at most sensitive regions when the heavy ion impregnates is looked into at different angles (θ) as well as azimuth (ϕ). This method makes it possible to assess how the device behaves for a variety of potential radiation directions that are pertinent to challenging operating conditions. Furthermore, several combinations of LET (2.41, 4.13, 4.94, 5.76, 10, 30, 50) is used to accurately assess the performance of the device at different θ and ϕ. For a broad range of LET, we have reported the transient drain current, collected charge, and heavy ion charge density. The results indicate that the maximum degradation occurs at ϕ = 0°, θ = 90°, ϕ = 90°, θ = 150° and ϕ = 150°, θ = 120° whereas the minimum response is observed at ϕ = 90°, θ = 60° and ϕ = 90°, θ = 90°. In order to demonstrate how sensitive these NSFETs are to angular radiation profiles, the analysis is further expanded to measure peak drain current and collected charge.
In recent times, there has been an immense amount of interest in the utilization of gallium oxide (Ga2O3) in power electronics because of the excellent figure of merit (FOM) values it exhibits, mostly as a consequence of its wide bandgap of almost 5 eV. Many different Ga2O3-based field-effect transistors (FETs) have been realized, and a number of devices have also been proposed in the literature. Among these devices, high electron mobility transistors (HEMTs) are particularly advantageous in realizing the high-power RF capabilities of Ga2O3, as they typically exhibit higher values of sheet carrier density (ns) and effective mobility (μeff). Of the proposed structures, the AlN/β-Ga2O3 polar HEMT is one of the most promising, with simulations indicating ns of the order 1013 cm-2 and excellent RF parameter values. In this work, we have performed a proof-of-concept simulation of an AlN/β−Ga2O3 polar HEMT, having gate length (LG) of 50 nm to maximize RF performance, with the aim of benchmarking this device’s performance and exploring its design space. We note poor subthreshold characteristics and aim to improve subthreshold slope (SS), ON-OFF current ratio (ION/IOFF) and drain-induced barrier lowering (DIBL) coefficient without significantly compromising the RF performance. To this end, we implement an (AlxGa1−x)2O3 back barrier layer to improve carrier confinement and mitigate OFF-state leakage current. SS and DIBL values of 122 mV/dec and 87 mV/V were obtained for an optimized structure having the back barrier, with an ON-OFF ratio (ION/IOFF) of the order 106−107. While the implementation of the back barrier initially produced improvement in the values of cutoff frequency (ft) and maximum oscillation frequency (fmax), the optimized structure having the best subthreshold performance exhibited lower ft and fmax values of 66.3 GHz and 74.8 GHz respectively, though these are still superior to the highest reported values for experimentally realized Ga2O3-based planar FETs. These results vindicate the interest in developing AlN/β−Ga2O3 polar HEMTs as reliable high-performance RF devices, while the improved subthreshold characteristics also increase the applicability of these devices for use in biosensors.
Organic field-effect transistors (OFETs) based on conjugated polymers are promising for flexible, low-cost electronics; however, their performance is often limited by interfacial trap states and disordered molecular packing. In this work, the combined influence of fabrication method (spin coating and UFTM), dielectric interface engineering (OTS and CYTOP), and molecular orientation on the charge transport characteristics of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2)-based thin film transistors is systematically investigated. The UFTM process produces highly aligned polymer films, yielding pronounced optical anisotropy with a dichroic ratio of ~ 6.5 at an optimized annealing temperature of 120 °C. The optimized UFTM CYTOP (ǁ) device exhibits a maximum field-effect mobility of ~2.8 × 10-³ cm² V-¹ s-¹, an on/off current ratio of ~ 4 × 10⁶, improved threshold voltage, reduced subthreshold swing, excellent device-to-device reproducibility, while retaining ~ 80% of its initial mobility after 60 days under ambient conditions. These findings demonstrate a simple, low-cost, and scalable fabrication strategy for improving the electrical performance and operational reliability of F8T2-based OFETs.
Single event upset (SEU) cross-section and total ionizing dose (TID) effects were studied at the 12-nm bulk FinFET technology node. In this paper, SEU rates of flip-flop (FF) designs with different threshold voltage (VT) options in a GF 12-nm bulk FinFET technology are investigated with alpha particles, protons, and heavy ions. Irradiation results indicate that various VT options of the transistors do not have a significant impact on SEU rates of the FFs at this technology node, while FFs with HVT transistors exhibit slightly higher cross-sections. Interestingly, LVT and RVT cells exhibit opposite trends when exposed to different LET particles. SPICE and TCAD simulations have been carried out to further analyze the experimental results. In addition, the total dose effects on ring oscillators (RO) designed with inverters, two-input NAND and NOR gates are also investigated with gamma sources. PDK-based SPICE simulations and qualitative TCAD simulations are used to support the interpretation of the measured VT-dependent SEU trends. In addition, total-ionizing-dose effects on ring oscillators designed with inverters, two-input NAND gates, and two-input NOR gates are investigated using Co-60 gamma irradiation. The results show negligible RO frequency degradation and only a small chip-current increase up to 300 krad, indicating strong circuit-level TID tolerance for the implemented two-fin standard-cell RO structures.
Threading screw dislocations (TSDs) in heteroepitaxial GaN introduce quasi-one-dimensional (1D) conductive filaments that penetrate the full device depth, constituting a primary source of reverse leakage current in vertical heterogeneous power devices. Conventional TCAD simulation approaches, which model defects as zero-dimensional point charges, cannot capture the stochastic lateral distribution of TSDs or their coupling to three-dimensional (3D) electric field distributions. This work proposes a cross-scale numerical framework that couples a 1D trap carrier transport with a 3D bulk drift-diffusion model through carrier exchange terms. Critical physical parameters are derived from the first-principle calculation of the single six-atom ring TSD core and calibrated against experimental data of GaN vertical diodes, achieving quantitative agreement across a temperature range of 210–470 K within a bias voltage range of 0–300 V. The calibrated framework is applied to a GaN oxide-gated vertical trench MOSFET, where the TSD lateral position is varied across 56 devices. Under the conservative worst-case assumption of a single-6-atom ring TSD core, the analysis reveals that stochastic dislocation placement produces an upper-bound TAT threshold voltage spread of 31 V for a 0.6 μm trench depth, and 71 V for a 0.9 μm trench. This twofold increase is driven by the lateral electric field non-uniformity near the trench corner, and motivates a reorientation of vertical GaN device design principles, where lateral field uniformity should be treated as a primary constraint alongside breakdown voltage.
The degradation behavior of 1200 V planar-gate 4H-SiC MOSFETs under 10 MeV proton irradiation was investigated by combining Geant4 energy-deposition simulation, electrical characterization, deep-level transient spectroscopy (DLTS) analysis, and double-pulse switching tests. Irradiation was performed at a fluence of 1×1012 cm−2. The simulation results show that energy deposition in the sensitive regions is dominated by ionizing effects. After irradiation, the device exhibits a pronounced negative threshold-voltage shift and longer turn-off delay. In addition, both the Cgs–Vgs and Cgd–Vgs characteristics shift toward lower gate voltage. Trap extraction from electrical measurements further shows that the increase in oxide-trapped charge is much larger than that in interface-trap density, indicating that the degradation in the gate-oxide/near-interface region is mainly governed by oxide-trapped charge buildup. Meanwhile, the off-state leakage current increases significantly after irradiation. DLTS results further reveal significant increases in the concentrations of the deep-level traps E2 (EC−0.72 eV) and E3 (EC−0.93 eV), which are considered to participate in trap-assisted leakage transport under reverse bias and thus contribute to leakage degradation.
The device integrity critically depends on the co-optimization of the electrostatic control and thermal management in device design and reliability. This work considers nanosheet-based Complementary FET (CFET) as a baseline configuration, with n-FET (N) sheets stacked atop p-FET (P) sheets. In CFET structure, the source/drain (S/D) spacer material and its length critically influence the device electrostatics and self-heating. To address this coupled behavior, using well-calibrated TCAD models, the critically engineered role of asymmetric dielectric spacer lengths made of dissimilar materials is investigated to co-optimize the device's electro-thermal characteristics. The asymmetric lengths of the source-side spacer (LSPS) and drain-side spacer (LSPD) vary from 3 nm to 7 nm, with 5 nm as the baseline value calibrated against experimental data. Increasing LSPD degrades ON current (ION) by 26.17% in nFET and 22.61% in pFET due to SHE. In turn, the figure of merit (FoM), defined as ION/Cgg, and the cut-off frequency (fT) improve by 15.03% (12.1%) and 17.58% (13.92%), respectively, in nFET (pFET) when LSPD increases while keeping LSPS fixed at 5 nm. Further, a semi-empirical model is developed to determine the differential change in ION of the proposed asymmetric spacer configurations. Finally, a single-transistor (1T) CFET-based inverter and a FO4 cell are designed to analyze the impact of proposed asymmetric spacer configurations on the speed-power trade-off, using HfO2 and SiO2 spacer materials to optimize fringe coupling, self-heating, and overshoot. Thus, the proposed study provides a pivotal design knob for achieving balanced electrostatic control, transient stability, and thermal reliability in scaled CFET devices.
The transfer characteristics of silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOS-FETs) are fundamental indicators relevant to their practical applications, with hysteresis serving as a critical measure of the interface defect density within the gate oxide layer. However, measurement delays pose challenges to the accurate extraction of these transfer characteristics. This study introduces an on-the-fly (OTF) technology to characterize dynamic transfer characteristics, effectively eliminating measurement delays and complex preconditioning operations. This advancement enables a more pronounced observation of hysteresis under continuous switching stress, providing a more realistic dynamic evaluation compared to conventional static measurements. Unlike previous studies, this research directly investigates the impact of various switching application configurations on extraction results and provides a physical basis for these findings. The results suggest an optimal stress configuration for the stable and maximized extraction of significant hysteresis, characterized by a lower switching voltage, an intentionally reduced switching speed, a lower temperature, and an increased gate voltage amplitude. Rather than serving as a direct online condition monitoring tool, this research aims to establish a robust offline characterization platform. This method bridges the gap between static testing and continuous dynamic operations, providing insight into the interface trap dynamics of SiC MOSFETs.
In this work, the parameters degradation and failure mechanisms of 1200V double-trench SiC MOSFETs under both single and repetitive surge current stresses has been systematically investigated. Experiments have been conducted at gate-source voltages (VGS) of 0 V, –5 V, and –10 V. The critical single-pulse surge current has been first determined using incremental single-surge stress until catastrophic failure. Repetitive surge tests have been then conducted at fixed current amplitudes corresponding to 90% and 60% of this critical value to evaluate cumulative, non-catastrophic degradation. Results demonstrate that the VGS significantly influences the surge capability of the device. As VGS becomes more negative, the threshold voltage shift increases significantly in the negative direction. Under single surge stress, the device at VGS = 0 V exhibits a surge tolerance approximately 45.45% lower than that at VGS = -5 V and -10 V due to stronger channel-assisted leakage conduction under the hybrid conduction condition. Under repetitive stress, the fewest surge cycles are observed for the device at VGS = 0 V, the same as single stress. The increase in surge cycles with VGS rising from -10 V to -5 V is attributed to the increase of the degree for channel opening, allowing more surge current flow through channel. It is revealed that device failures under single surge stress are primarily caused by metal migration and active region breakdown, leading to three-terminal short circuit. Variations in failure mechanisms are observed under different repetitive surge conditions. Localized interlayer dielectric (ILD) and metallization damage near the termination region is associated with degradation of the drain–source blocking capability at the 90% stress level, while the combined effect of gate oxide fracture and ILD damage contributes to leakage paths at the 60% stress level. These findings provide valuable insights for the reliability optimization and application of double-trench SiC MOSFETs in high-power systems.
In this paper, we present a new physical mechanism related to the voltage drop induced by heavy-ion-induced Single Event Upset (SEU) in the device structure, and propose an analytical methodology for this effect in memory semiconductors using the Partial Insulator in a Buried Channel Array Transistor (Pi-BCAT). In previous studies, Pi-BCAT was shown to improve Gate-Induced Drain Leakage (GIDL) and Row Hammer Effect (RHE) characteristics compared to BCAT by inserting an insulator in the lower region of the BCAT Storage Node (SN). However, in a space environment, SEU can occur due to high energy particle strikes, and GIDL and RHE characteristics can be additionally degraded as a result. This can induce abnormal inversion (bit-flip) of stored information in memory semiconductors, critically affecting system reliability. Therefore, in this study, the effect of charge generated by heavy ion irradiation on the SN voltage drop of BCAT and Pi-BCAT is analyzed. In addition, trap, which has been regarded as a conventional reliability degradation factor, is reinterpreted, and it is shown that the SN voltage drop due to SEU can be mitigated through Trap-Assisted Tunneling Recombination (TAT Recombination), and this is defined as Trap-Assisted SEU Mitigation (TASM). When trap is present, electrons generated by heavy ions are annihilated by TAT Recombination, and it is confirmed that the SN voltage drop is improved by 73% compared to the case without trap. The proposed Pi-BCAT suppresses the funnel effect compared to the conventional BCAT, and improves the voltage drop variation amount by 39% by TASM operating effectively in the strengthened electric field region above Pi. Therefore, it is confirmed that the Pi-BCAT structure improves the SN voltage drop and enhances SEU tolerance compared to the conventional BCAT.
This paper explores the structural design and three-dimensional TCAD-based reliability assessment of an E-shaped CombFET optimized for advanced nanoscale CMOS technology nodes. The proposed architecture employs three stacked nanosheet channels interconnected through an asymmetric fin-like interbridge, forming an E-shaped topology that enhances gate to channel coupling while maintaining structural simplicity. Device level simulations are carried out using Sentaurus TCAD at a 12 nm gate length to evaluate electrostatic integrity and material induced reliability trends. In comparison with conventional NanosheetFET, CombFET, and TreeFET architectures, the proposed E-CombFET demonstrates improved ON-state drive capability and maintaining sub-threshold swing, indicating enhanced electrostatic control without degradation in subthreshold characteristics. Temperature dependent simulations conducted from 150 K to 450 K across different spacer materials reveals a moderate decrease in (ION) and a corresponding increase in (IOFF) indicating thermally resilient operation with acceptable switching characteristics. In addition to performance improvement the proposed E-CombFET demonstrates favorable analog conductance modulation characteristics indicating its potential suitability for neuromorphhic computing applications.
