Advances in SEM imaging voltage contrast of advanced technology node SRAMs are discussed. The use of large apertures, careful choice of plane of polish, and secondary electron detection modes in the SEM column may enable the triggering of Capacitive Coupling Voltage Contrast. An AI segmentation model that provides a quantitative quality factor for the images is presented.

A simple method for the in-situ examination of device turn-on in an Insulated Gate Bipolar Transistor (IGBT) is presented. A Ga + Focused Ion Beam (FIB) was used to mill away a wedge-shaped section from the material so as to leave the exposed devices operable by the surface gate and emitter contact pads. Through this window, a series of nanoprobing-based measurements were undertaken. Sensitive, Electron Beam Induced Current (EBIC) measurements strongly delineated both of the p/n junctions in the exposed surface, both those between the N+ emitter and the P-well or body, and between this P-body and N-drift region. Next, the gate voltages were varied and a series of EBIC images were taken of the body/drift depletion zone. Quantitative plots of the same gave an indication of when the insulated gate portion of the device turned on. Finally, a follow-up experiment showed the effect of applied bias on Active Voltage Contrast (AVC) of the junction. The results point to a method for examination of junctions and their behavior under gate bias with very little sample preparation. The results also ease some concerns about the use of GaFIB in sample prep for junction examination in failure analysis, given the detailed work that was possible.

Results involving the use of a single nanoprobing contact are presented, on both a SiC planar MOSFET device, and a small system-in package. In both cases, mechanical polished samples were prepared, and then probed with a single contact. For the SiC MOSFET, the depletion zones were imaged while the samples were mounted on a 45 ° stub. Discussion of the different signals generated from Passive Voltage Contrast (PVC) and Electron Beam Induced Current (EBIC), as well as possible artifacts of sample grounding, are provided. For the package, Electron Beam Absorbed Current (EBAC) provided indication of connected features within the sample. The experiment showed the capability of measuring features across three orders of magnitude in size.

Methods for evaluation of junction in power semiconductor devices are discussed. An Insulated Gate Bipolar Transistor (IGBT) chip was selected for the experiment. Samples were alternatively mechanically polished, cleaved, or in a third case, sectioned with an experimental FIB (Focused Ion Beam) section. From here, sensitive Electron Beam Induced Current (EBIC) measurements were undertaken and results were compared. There was little difference in the ability to detect depletion zones between the techniques, indicating that Ga+ contamination or amorphization from the FIB did not prevent the collection of useful data from the p/n junctions. During the course of experimentation, it was determined that the pixel dwell time during electron beam stimulation had a strong effect on removing artifacts and increasing the contrast of the result. In the optimized analysis, the EBIC work crisply imaged the depletion zones of not only the P body / N- drift regions, but also the N+ / body regions in the same image. Additional observations were made to compare the different physical extents of the implant regions by Passive Voltage Contrast (PVC) versus the depletion zones from the EBIC results.

Measuring surface conduction points is a well-established analytical technique in SRAM failure analysis. A novel workflow and system have been developed that makes use of an Atomic Force Microscope (AFM) inside a Scanning Electron Microscope (SEM) and is capable of using standard laser deflection based probe tips. New results are provided on an 8T SRAM cell in 7 nm technology which demonstrate the ability to measure nFET, pFET, and gate contacts simultaneously with one scan, and with a topography measurement. A second analysis was performed to demonstrate the ability of the electron beam, combined with use of the AFM diamond tip as a scalpel, to expose subsurface layers and greatly improve current data. Furthermore, the system being in vacuum provides additional benefits in eliminating confounding effects.

An intentionally overstressed fin defect was created in 5 nm technology. EBIC analysis with 0.5 kV electron beam stimulation enabled early detection of the defect during overstress experiments. EBIRCH analysis, again at 0.5 kV was able to isolate the exact spot of the fail in a multi-fin device. Additional EBIC scans at various kVs were also able to isolate the failing fin, located close to the EBIRCH spot, and provided insights on how to use Monte Carlo scattering models to predict the optimal beam energy to find defects via EBIC. This approach could be applied to fails in 5 nm or systems with delicate structures.

Microscopic imaging and characterization of semiconductor devices and material properties often begin with a sample preparation step. A variety of sample preparation methods such as mechanical lapping and broad ion beam (BIB) milling have been widely used in physical failure analysis (FPA) workflows, allowing internal defects to be analyzed with high-resolution scanning electron microscopy (SEM). However, these traditional methods become less effective for more complicated semiconductor devices, because the cross-sectioning accuracy and reliability do not satisfy the need to inspect nanometer scale structures. Recent trends on multi-chip stacking and heterogenous integration exacerbate the ineffectiveness. Additionally, the surface prepared by these methods are not sufficient for high-resolution imaging, often resulting in distorted sample information. In this work, we report a novel correlative workflow to improve the cross-sectioning accuracy and generate distortion-free surface for SEM analysis. Several semiconductor samples were imaged with 3D X-ray microscopy (XRM) in a non-destructive manner, yielding volumetric data for users to visualize and navigate at submicron accuracy in three dimensions. With the XRM data to serve as 3D maps of true package structures, the possibility to miss or destroy the fault regions is largely eliminated in PFA workflows. In addition to the correlative workflow, we will also demonstrate a proprietary micromachining process which is capable of preparing deformation-free surfaces for SEM analysis.

An investigation of shorting defects in SRAM structures by means of low-voltage EBIC is presented and the location of the defect was compared to the one isolated with EBIRCH. A pulldown device in 7 nm technology was intentionally overstressed, and the shorting location isolated with EBIRCH at 500 V. Then a series of EBIC investigations at very low voltage were undertaken in an experiment to isolate the problem. It was determined that some information about the nature of the defect was clear at beam landing energies as low as 150 eV.

A workflow for efficient analysis of defects in an SRAM array is proposed. After delayering, the transistors responsible for a specific single cell failure are localized using a nanoprobing system loaded into a dual-beam FIB chamber. The failing area is analyzed by the nanoprobing system with the EBIRCH (Electron Beam Induced Resistance CHange) technique. Then a high-resolution backscatter image is undertaken to look in-plane for certain types of defects. This is followed by the preparation of a TEM lamella inside the same chamber. The analysis is preceded by the use of a STEM detector to take high-resolution cross-sectional images of the defect. Rotated views of the specimen may then be taken to form a 3D tomographic image. The proposed workflow makes optimum use of a single chamber analytical tool. Example images from a recent analysis performed on 14 nm bulk technology sample are provided.

a new cross-section workflow for improved access to buried structures within electronic devices has been developed. A focused-ion beam scanning-electron microscope (FIB-SEM) system has been integrated by attaching a femtosecond laser to the loadlock chamber, enabling rapid site-specific preparation of internal device details. Evidence is provided that compared with traditional techniques, this new workflow enabled by the Crossbeam laser FIB-SEM offers improved speed and productivity, while simultaneously delivering more precise dimensional sampling and reduced damage to the surrounding area.

In order to fully understand the full breadth of technology problems that may affect yield or performance in advanced technologies, junctions need to be characterized in greater detail. Rather than extensive lamella preparation, or serial cross-sectioning, a fresh approach is needed. Results showing EBIC analysis of SRAMs delayered to contact layer are provided. By probing different nodes of the SRAM cell at different beam landing energies, a wide variety of device phenomena may be explored. This technique can empower the rapid scanning of multiple cell blocks and catch details that passive voltage contrast at the contact level may miss. A table of results is provided.

Abstract Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.

During technology development, leakage during inline or bench test of a p+ SiGe active areas short monitor structures may produce false short signal or hide real defect induced leakage. This paper investigates different sources of leakages - defects in SiGe, pressure due to tester probe on test pads, silicidation issues and boron P+ and arsenic N halo ion implants dose/energy. Some changes to mitigate the extraneous leakage are also presented in the paper.

Presented here is an analysis of photoresist profile and feature control performance for high-energy well implant lithography as it is implemented in microelectronic devices, specifically SRAMs, at the 45 and 65nm nodes. As device designs become increasingly smaller to the tune of Moore's Law, deep well implant lithography specifications become more and more stringent, and issues related to lateral implant scattering that were more trivial for more relaxed designs begin to make significant contributions to photoresist feature uniformity and implant profile control. Simplified process assumptions that overlook such non-ideal implant phenomena can result in an overestimation of process latitude. Undesirable variability derived from the implantation, lithography, and substrate associated with a deep well formation process can degrade implantation profiles and have adverse effects on device electrical performance. Mechanisms for these adverse effects such as implant scattering and implant straggle will be explored followed by their relationships to process tolerance and electrical performance. Emphasis will be placed on evaluating the optimum photoresist feature profile for a given process and determining its true process latitude as opposed to "centering" a feature in a device layout during design. Finally, challenges confronting process control methods for high-aspect ratio implant mask features will be discussed followed by some proposed process improvement suggestions.