A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.

A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5μm 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating ΣΔ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.